An efficient ultra-low-power and superior performance design of ternary half adder using CNFET and gate-overlap TFET devices
S Vidhyadharan, SS Dan - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This paper presents a novel ultra-low power yet high-performance device and circuit design
paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs …
paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs …
A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder
S Vidhyadharan, SS Dan, R Yadav… - International Journal of …, 2020 - Taylor & Francis
Recent researches have indicated that the gate-overlap tunnel FETs (GOTFETs) exhibit
double the on-currents I on and one-tenth the off-currents I off than the equally sized …
double the on-currents I on and one-tenth the off-currents I off than the equally sized …
An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger
S Vidhyadharan, SS Dan, R Yadav… - Microelectronics Journal, 2020 - Elsevier
This paper introduces an innovative Gate-Overlap Tunnel FET (GOTFET) device which is an
advanced TFET engineered to yield around double the on current I on, while the off current I …
advanced TFET engineered to yield around double the on current I on, while the off current I …
Gate-Overlap Tunnel Field-Effect Transistors (GOTFETs) for Ultra-Low-Voltage and Ultra-Low-Power VLSI Applications
S Vidhyadharan, SS Dan - Microelectronics and Signal Processing, 2021 - taylorfrancis.com
The advancement in complementary metal oxide semiconductor (CMOS) technology during
the last few decades has enabled scaling down of the metal oxide semiconductor field-effect …
the last few decades has enabled scaling down of the metal oxide semiconductor field-effect …