Benchmarking of multi-bridge-channel FETs toward analog and mixed-mode circuit applications
In this study, for the very first time developing of n-and p-type 3-D single-channel (SC)
FinFET and gate-all-around (GAA) Multi-Bridge-Channel FETs (MBCFET) like nanowire FET …
FinFET and gate-all-around (GAA) Multi-Bridge-Channel FETs (MBCFET) like nanowire FET …
Comparative analysis & study of various leakage reduction techniques for short channel devices in junctionless transistors: A review and perspective
Leakage current in a MOS device has become a bottleneck with the technological growth of
semiconductor industry. As the device is scaled down to sub nano meter regime, leakage …
semiconductor industry. As the device is scaled down to sub nano meter regime, leakage …
Charge-plasma based process variation immune junctionless transistor
In this letter, we report for the first time a distinctive approach of implementing a junctionless
transistor (JLT) without doping (doping-less) the ultrathin silicon film. A charge-plasma …
transistor (JLT) without doping (doping-less) the ultrathin silicon film. A charge-plasma …
Direct Rashba spin-orbit interaction in Si and Ge nanowires with different growth directions
We study theoretically the low-energy hole states in Si, Ge, and Ge/Si core/shell nanowires
(NWs). The NW core in our model has a rectangular cross section, the results for a square …
(NWs). The NW core in our model has a rectangular cross section, the results for a square …
A comprehensive analysis of junctionless tri-gate (TG) FinFET towards low-power and high-frequency applications at 5-nm gate length
VB Sreenivasulu, V Narendar - Silicon, 2021 - Springer
Abstract Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate
lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless …
lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless …
Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes
VB Sreenivasulu, V Narendar - AEU-International Journal of Electronics …, 2022 - Elsevier
Silicon (Si) ultrathin junctionless (JL) n-FinFET with LG= 3 nm and 1 nm are explored for the
first time by invoking Hf x Ti 1-x O 2 based high-k gate dielectric. The 3D device performance …
first time by invoking Hf x Ti 1-x O 2 based high-k gate dielectric. The 3D device performance …
Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications
This work covers the impact of dual metal gate engineered Junctionless MOSFET with
various high-k dielectric in Nanoscale circuits for low power applications. Due to gate …
various high-k dielectric in Nanoscale circuits for low power applications. Due to gate …
Semianalytical model of the subthreshold current in short-channel junctionless symmetric double-gate field-effect transistors
A Gnudi, S Reggiani, E Gnani… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
A 2-D semianalytical solution for the electrostatic potential valid for junctionless symmetric
double-gate field-effect transistors in subthreshold regime is proposed, which is based on …
double-gate field-effect transistors in subthreshold regime is proposed, which is based on …
Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length
VB Sreenivasulu, V Narendar - AEU-International Journal of Electronics …, 2021 - Elsevier
In this paper, for the first time, we have investigated the DC and analog/RF performance
metrics of 3 nm gate length (LG) silicon-on-insulator (SOI) FinFET using Hf x Ti 1− x O 2 high …
metrics of 3 nm gate length (LG) silicon-on-insulator (SOI) FinFET using Hf x Ti 1− x O 2 high …
Design and deep insights into sub-10 nm spacer engineered junctionless FinFET for nanoscale applications
N Vadthiya - ECS journal of solid state science and technology, 2021 - iopscience.iop.org
In this paper, we have studied the impact of various dielectric single-k (Sk) and dual-k (Dk)
spacers on optimized Junctionless (JL) FinFET at nano-regime by using hetero-dielectric …
spacers on optimized Junctionless (JL) FinFET at nano-regime by using hetero-dielectric …