[HTML][HTML] Effect of hyper-threading in latency-critical multithreaded cloud applications and utilization analysis of the major system resources
Multithreaded latency-critical applications represent an important subset of workloads
running on public cloud systems. Most of these systems deploy powerful computing servers …
running on public cloud systems. Most of these systems deploy powerful computing servers …
A reusable characterization of the memory system behavior of spec2017 and spec2006
The SPEC CPU Benchmarks are used extensively for evaluating and comparing
improvements to computer systems. This ubiquity makes characterization critical for …
improvements to computer systems. This ubiquity makes characterization critical for …
WL-WD: Wear-leveling solution to mitigate write disturbance errors for phase-change memory
Phase-change memory (PCM) is a promising non-volatile memory device due to its
attractive properties such as fast access time and byte-addressability. However, PCM is still …
attractive properties such as fast access time and byte-addressability. However, PCM is still …
BALANCER: bandwidth allocation and cache partitioning for multicore processors
The management of shared resources in multicore processors is an open problem due to
the continuous evolution of these systems. The trend toward increasing the number of cores …
the continuous evolution of these systems. The trend toward increasing the number of cores …
ZEC ECC: A Zero-byte Eliminating Compression Based ECC Scheme for DRAM Reliability
JH Kwon, HK Bae, YS Lee, YH Gong… - IEEE Access, 2024 - ieeexplore.ieee.org
As DRAM cells continue to shrink, the conventional single error correction and double error
detection (SECDED) code is not sufficient to provide DRAM error resilience. To satisfy …
detection (SECDED) code is not sufficient to provide DRAM error resilience. To satisfy …
Hycsim: A rapid design space exploration tool for emerging hybrid last-level caches
Recent years have seen a rising trend in the exploration of nonvolatile memory (NVM)
technologies in the memory subsystem. Particularly in the cache hierarchy, hybrid last-level …
technologies in the memory subsystem. Particularly in the cache hierarchy, hybrid last-level …
L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime
Several emerging non-volatile (NV) memory technologies are rising as interesting
alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM …
alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM …
An application-oriented approach to designing hybrid cpu architectures
A Yue, S Mehta - … on Performance Analysis of Systems and …, 2023 - ieeexplore.ieee.org
Hybrid CPUs have recently launched in desktop and laptop devices with the goal of
increasing core count at manageable power consumption. These CPUs contain …
increasing core count at manageable power consumption. These CPUs contain …
Improving the Representativeness of Simulation Intervals for the Cache Memory System
Accurate simulation techniques are indispensable to efficiently propose new memory or
architectural organizations. As implementing new hardware concepts in real systems is often …
architectural organizations. As implementing new hardware concepts in real systems is often …
Temporal characterization of memory access behaviors in SPEC CPU2017 workloads: Analysis and synthesis
The SPEC CPU2017 benchmark suite has received wide attention in both academia and
industry. However, few work have studied the memory behaviors in SPEC CPU2017 …
industry. However, few work have studied the memory behaviors in SPEC CPU2017 …