On the acceleration of test generation algorithms

Fujiwara, Shimono - IEEE Transactions on Computers, 1983 - ieeexplore.ieee.org
In order to accelerate an algorithm for test generation, it is necessary to reduce the number
of backtracks in the algorithm and to shorten the process time between backtracks. In this …

[PDF][PDF] Critical path tracing-an alternative to fault simulation

M Abramovici, PR Menon, DT Miller - Papers on Twenty-five years of …, 1988 - dl.acm.org
We present an alternative to fault simulation, referred to as critical path tracing, that
determines the faults detected by a set of tests using a backtracing algorithm starting at the …

Gentest: an automatic test-generation system for sequential circuits

WT Cheng, TJ Chakraborty - Computer, 1989 - ieeexplore.ieee.org
A description is given of Gentest, with emphasis on STG2, a sequential test generator that
uses the Back test-generation algorithm and the Split value model. The performance of …

[PDF][PDF] Search algorithms for satisfiability problems in combinational switching circuits

J Marques-Silva - 1995 - eprints.soton.ac.uk
ABSTRACT SEARCH ALGORITHMS FOR SATISFIABILITY PROBLEMS IN
COMBINATIONAL SWITCHING CIRCUITS by João Paulo Marques da Silva Chair: Karem A …

An effective test generation system for sequential circuits

R Marlett - 23rd ACM/IEEE Design Automation Conference, 1986 - ieeexplore.ieee.org
This paper describes a test generation system capable of high fault coverage in complex
sequential circuits. Sequential logic is efficiently processed by a unidirectional time flow …

A method to calculate necessary assignments in algorithmic test pattern generation

J Rajski, H Cox - Proceedings. International Test Conference …, 1990 - ieeexplore.ieee.org
The authors present a novel test pattern generation algorithm which uses the concept of
necessary assignments to reduce or eliminate backtracking in automatic test pattern …

B-algorithm: A behavioral test generation algorithm

CH Cho, JR Armstrong - Proceedings., International Test …, 1995 - ieeexplore.ieee.org
A behavioral test generation algorithm (called the B-algorithm) is presented which generates
tests directly from behavioral VHDL circuit descriptions using three types of behavioral faults …

Delay test generation. ii. algebra and algorithms

VS Iyengar, BK Rosen… - … Test Conference 1988 …, 1988 - ieeexplore.ieee.org
For pt. I see ibid., p. 857-66 (1988). A novel algebra is introduced for delay test generation.
The algebra combines the nine natural logic values (00, 01, 0X, 10, 11, 1X, X1, XX) with …

Design of modular digital circuits for testability

A Kusiak, CC Huang - IEEE Transactions on Components …, 1997 - ieeexplore.ieee.org
Modular products and reconfigurable testing processes are crucial in modern
manufacturing. This paper discusses the concept of product modularity, test modules of …

A framework and method for hierarchical test generation

JD Calhoun, F Brglez - … on computer-aided design of integrated …, 1992 - ieeexplore.ieee.org
The authors present an algorithm for hierarchical test generation based on module-oriented
decision making (MODEM). The algorithm deals with combinational logic modules and the …