A method includes receiving an Error Correction Code (ECC) code word, which includes
multiple encoded bits that represent data and have a bit order. Multiple subsets of the …

US8429498B1 - Dual ECC decoder - Google Patents US8429498B1 - Dual ECC decoder -
Google Patents Dual ECC decoder Download PDF Info Publication number US8429498B1 …

7,334, 181 7,343,539 7,480,845 7,499.490 7,734,988 7,890,844 7,966,548 7,984,368
8,006,162 8, 117,523 8,132,072 8,161,363 8,209,592 8,239,746 8,386,906 2006/02O3765 …

US8495450B2 - System and method for structured LDPC code family with fixed code length
and no puncturing - Google Patents US8495450B2 - System and method for structured …

(57) ABSTRACT A low density parity check (LDPC) family of codes is con structed by:
determining a protograph for a mother code for the LDPC family of codes. The protograph is …

An apparatus and method decode LDPC code. The apparatus includes a memory and a
number of LDPC processing elements. The memory is configured to receive a LDPC …

(57) ABSTRACT A receiver for use in a wireless communications network capable of
decoding encoded transmissions. The receiver comprises receive path circuitry for receiving …

This application a 35 USC S 111 (a) continuation-in-part of PCT international application
number PCT/US2009/044899 filed on May 21, 2009, incorporated herein by refer ence in its …

A technique for decoding low-density parity check codes includes performing a combined
check node and variable node calculation. Decoding is initialized using channel likelihood …

138 tured check symbols selected from among check symbols of the first code words. A
mother decoder, which is designed to decode the mother ECC by exchanging messages …