Computer architects employ a series of performance optimizations at the micro-architecture
level. These optimizations are meant to be invisible to the programmer but they are implicitly …

Store misses cause significant delays in shared-memory multiprocessors because of limited
store buffering and ordering constraints required for proper synchronization. Today …

This paper presents NoSQ (short for No Store Queue), a microarchitecture that performs
store-load communication without a store queue and without executing stores in the outof …

Conventional processors use a fully-associative store queue (SQ) to implement store-load
forwarding. Associative search latency does not scale well to capacities and bandwidths …

Modern processors use CAM-based load and store queues (LQ/SQ) to support out-of-order
memory scheduling and store-to-load forwarding. However, the LQ and SQ scale poorly for …

This paper describes a scalable, low-complexity alternative to the conventional load/store
queue (LSQ) for superscalar processors that execute load and store instructions …

Optimizing the common case has been an adage in decades of processor design practices.
However, as the system complexity and optimization techniquespsila sophistication have …

Conventional load/store queues (LSQs) are an impediment to both power-efficient execution
in superscalar processors and scaling tolarge-window designs. In this paper, we propose …

Because they are based on large, content-addressable memories, load-store queues
(LSQs) present implementation challenges in superscalar processors. In this paper, we …

Recently, higher education has seen an increasing emphasis on the prominent role of
computational thinking in all disciplines. Computational thinking is advocated as not only a …