Bulk‐Switching Memristor‐Based Compute‐In‐Memory Module for Deep Neural Network Training

Y Wu, Q Wang, Z Wang, X Wang, B Ayyagari… - Advanced …, 2023 - Wiley Online Library
The constant drive to achieve higher performance in deep neural networks (DNNs) has led
to the proliferation of very large models. Model training, however, requires intensive …

Neural architecture search for in-memory computing-based deep learning accelerators

O Krestinskaya, ME Fouda, H Benmeziane… - Nature Reviews …, 2024 - nature.com
The rapid growth of artificial intelligence and the increasing complexity of neural network
models are driving demand for efficient hardware architectures that can address power …

Flexible neuromorphic devices based on two-dimensional transition metal dichalcogenides

XQ Ma, G Ding, W Niu, Z Jia, ST Han… - IEEE Journal on …, 2023 - ieeexplore.ieee.org
The development of artificial intelligence has continuously amplified the demand for
neuromorphic computing and memory. However, the separation of computing and memory …

Kernel Shape Control for Row-Efficient Convolution on Processing-In-Memory Arrays

J Rhe, KE Jeon, JC Lee, S Jeong… - 2023 IEEE/ACM …, 2023 - ieeexplore.ieee.org
Processing-in-memory (PIM) architectures have been highlighted as one of the viable
solutions for faster and more power-efficient convolutional neural networks (CNNs) …

TT-CIM: Tensor Train Decomposition for Neural Network in RRAM-Based Compute-in-Memory Systems

FH Meng, Y Wu, Z Zhang, WD Lu - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Compute-in-Memory (CIM) implemented with Resistive-Random-Access-Memory (RRAM)
crossbars is a promising approach for accelerating Convolutional Neural Network (CNN) …

An 11T1C Bit-Level-Sparsity-Aware Computing-in-Memory Macro With Adaptive Conversion Time and Computation Voltage

Y Lin, Y Li, H Zhang, H Ma, J Lv… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
A static random-access memory (SRAM)-based computing-in-memory (CiM) is a promising
architecture for efficiently performing high-precision integer (INT) multiplication and …

KERNTROL: Kernel Shape Control Toward Ultimate Memory Utilization for In-Memory Convolutional Weight Mapping

J Rhe, KE Jeon, JC Lee, S Jeong… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Processing-in-memory (PIM) architectures have been highlighted as one of the most viable
options for faster and more power-efficient computation. Paired with a convolutional weight …

Aging Aware Retraining with a Sparse Update for Neuromorphic Computing

A Radhakrishnan, A James - 2023 IEEE International …, 2023 - ieeexplore.ieee.org
A low-power system with minimal area and high inference accuracy defines the performance
of the neural network accelerators. This tradeoff between accuracy and hardware …

A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI …

L Wu, C Zhao, J Wang, X Yu, S Chen… - 2024 29th Asia and …, 2024 - ieeexplore.ieee.org
Computing-in-memory (CIM) is a promising technique for hardware acceleration of neural
networks (NNs) with high performance and efficiency. However, conventional dense …

High-Performance Process-in-Memory Architectures Design and Security Analysis

Z Wang - 2024 - deepblue.lib.umich.edu
The performance of processor-centric von Neumann architectures is greatly hindered by
data movement between memory and processor, especially when encountering data …