High-κ gate dielectrics like HfO2 and HfSiO (N) are considered for the replacement of SiO2
and SiON layers in advanced complementary metal–oxide–semiconductor (MOS) devices …

For the first time, ultra low I OFF (16.5 pA/mum) and high I ON N, P (2.27 mA/mum and 1.32
mA/mum) currents are obtained with a multi-channel CMOSFET (MCFET) architecture on …

To analyze the reliability of semiconductor transistors, changes in the performance of the
devices during operation are evaluated. A prominent effect altering the device behavior are …

A simple analytical model that describes MOSFET operation in saturation from subthreshold
to strong inversion is used to derive a new formulation of the intrinsic switching delay of the …

A new mobility degradation specific to short channel MOSFETs is studied and elucidated.
Pocket implants/dopants pile-up, interface states/oxide charges, remote Coulomb scattering …

In this article, a reliable drain-extended (De) fin-shaped field-effect transistor (DeFinFET)
with improved thermal performance and electrical performance is proposed for high-voltage …

Abstract 28 nm FD-SOI technology is electrically characterized aiming at cryogenic
applications. Electrostatics and transport are evaluated and compared while lowering …

In this work the analogue performance of 50nm gate length FinFETs is investigated under
static and dynamic conditions up to 110GHz. The fin width is shown to have a large impact …

Three-and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with
a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D …

According to Moore's Law, not only does the number of transistors in an integrated circuit
double every two years, but transistor size also decreases at a predictable rate. At the rate …