Three-dimensional integrated circuit design
To the observer, it would appear that New York city has a special place in the hearts of
integrated circuit (IC) designers. Manhattan geometries, which mimic the blocks and streets …
integrated circuit (IC) designers. Manhattan geometries, which mimic the blocks and streets …
Yield enhancement for 3D-stacked ICs: Recent advances and challenges
Three-dimensional (3D) integrated circuits (ICs) that stack multiple dies vertically using
through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The …
through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The …
TSV-based 3-D ICs: Design methods and tools
Vertically integrated circuits (3-D ICs) may revitalize Moore's law scaling which has slowed
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …
Comparing through-silicon-via (TSV) void/pinhole defect self-test methods
Y Lou, Z Yan, F Zhang, PD Franzon - Journal of Electronic Testing, 2012 - Springer
Three methods have been proposed to test Through-Silicon-Vias (TSV) electrically prior to
3D integration. These test methods are (1) sense amplification;(2) leakage current monitor; …
3D integration. These test methods are (1) sense amplification;(2) leakage current monitor; …
Clock tree synthesis for low cost pre-bond testing of 3D integrated circuits
To enable low cost pre-bond testing for a three-dimensional (3D) integrated circuit, a
backbone die may have a fully connected two-dimensional (2D) clock tree and one or more …
backbone die may have a fully connected two-dimensional (2D) clock tree and one or more …
Resonant clock synchronization with active silicon interposer for multi-die systems
This paper presents the integration of resonant clocking to multi-die architectures to
synchronize individual chiplets connected through an active silicon interposer. The …
synchronize individual chiplets connected through an active silicon interposer. The …
Clock tree synthesis for TSV-based 3D IC designs
TY Kim, T Kim - ACM Transactions on Design Automation of Electronic …, 2011 - dl.acm.org
For the cost-effective implementation of clock trees in through-silicon via (TSV)-based 3D IC
designs, we propose core algorithms for 3D clock tree synthesis. For a given abstract tree …
designs, we propose core algorithms for 3D clock tree synthesis. For a given abstract tree …
Through-silicon via fault-tolerant clock networks for 3-D ICs
Clock network synthesis is one of the most important and challenging problems in 3-D ICs.
The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with …
The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with …
Fault-tolerant 3D clock network
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The
clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with …
clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with …
Fault-tolerant unit and method for through-silicon via
(57) ABSTRACT A fault-tolerant unit and a fault-tolerant method for through silicon via (TSV)
are provided. The fault-tolerant unit includes TSV structures TSV1-TSVn, nodes N1-N1 …
are provided. The fault-tolerant unit includes TSV structures TSV1-TSVn, nodes N1-N1 …