Multi-tier cache placement mechanism

J Wang, PS Ramrakhyani, W Wang… - US Patent …, 2020 - Google Patents
Storage of data in a cache system is controlled by a cache monitor. A cache line is filled in
response to a memory instruction from a cache client. The cache monitor includes a …

Bypass predictor for an exclusive last-level cache

Y Tian, T Nakra, V Sinha, H Le - US Patent 11,113,207, 2021 - Google Patents
A system and a method to allocate data to a first cache increments a first counter if a reuse
indicator for the data indicates that the data is likely to be reused and decremented the …

Victim allocations in shared system cache

S Gupta, PR Subramoniam - US Patent 10,963,392, 2021 - Google Patents
(57) ABSTRACT A system and method for efficiently handling data selected for eviction in a
computing system. In various embodiments, a computing system includes one or more …

Techniques for efficiently transferring data to a processor

A Kerr, J Choquette, X Qiu, O Paranjape… - US Patent …, 2024 - Google Patents
A technique for block data transfer is disclosed that reduces data transfer and memory
access overheads and significantly reduces multiprocessor activity and energy …

Cache management circuits for predictive adjustment of cache control policies based on persistent, history-based cache control information

RM Al Sheikh, A Perais, MS McIlvaine - US Patent 11,334,488, 2022 - Google Patents
A cache management circuit that includes a predictive adjustment circuit configured to
predictively generate cache control information based on a cache hit-miss indicator and the …

Bypass predictor for an exclusive last-level cache

Y Tian, T Nakra, V Sinha, H Le - US Patent 11,609,858, 2023 - Google Patents
A system and a method to allocate data to a first cache increments a first counter if a reuse
indicator for the data indicates that the data is likely to be reused and decremented the …

Filtering micro-operations for a micro-operation cache in a processor

M Scrbak, M Islam, J Kalamatianos… - US Patent 11,726,783, 2023 - Google Patents
A processor includes a micro-operation cache having a plurality of micro-operation cache
entries for storing micro-operations decoded from instruction groups and a micro-operation …

Techniques for efficiently transferring data to a processor

A Kerr, J Choquette, X Qiu, O Paranjape… - US Patent …, 2023 - Google Patents
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et al. 8.381. 203 B1 2/2013 Beylin et al. 8,555,035 B1 10/2013 Patney et al. 9069664 B2 …

High performance synchronization mechanisms for coordinating operations on a computer system

O Giroux, J Choquette, R Krashinsky… - US Patent …, 2023 - Google Patents
To synchronize operations of a computing system, a new type of synchronization barrier is
disclosed. In one embodiment, the disclosed synchronization barrier provides for certain …

Method and apparatus for buffering data blocks, computer device, and computer-readable storage medium

K Zhou, Y Zhang, H Wang, YG Ji, B Cheng - US Patent 11,461,239, 2022 - Google Patents
A method and apparatus for caching a data block are provided. The method includes:
obtaining, from a terminal, an access request for requesting access to a first data block; …