[PDF][PDF] 一种基于纳米级CMOS 工艺的互连线串扰RLC 解析模型
朱樟明， 钱利波， 杨银堂 - 物理学报, 2009 - wulixb.iphy.ac.cn
基于纳米级CMOS 工艺, 综合考虑电容耦合与电感耦合效应, 提出了分布式RLC
耦合互连解析模型. 采用函数逼近理论与降阶技术, 在斜阶跃输入信号下提出了受扰线远端的 …
耦合互连解析模型. 采用函数逼近理论与降阶技术, 在斜阶跃输入信号下提出了受扰线远端的 …
[PDF][PDF] Encoding schemes for reduction of power dissipation, crosstalk and delay in VLSI interconnects: A Review
SK Verma, BK Kaushik - International Journal of Recent Trends in …, 2010 - academia.edu
This paper reviews different encoding schemes for reduction of power dissipation, crosstalk
noise and delay. Crosstalk is aggravated by enhanced switching activity which is often main …
noise and delay. Crosstalk is aggravated by enhanced switching activity which is often main …
Effect of aggressor driver width on crosstalk for static and dynamic switching of victim line
DK Sharmal, BK Kaushik… - … Conference on Computer …, 2010 - ieeexplore.ieee.org
In DSM technology, unintended interactions between signals propagating through
interconnect turn out to be critical design concern. At technology nodes below 0.25 μm, the …
interconnect turn out to be critical design concern. At technology nodes below 0.25 μm, the …
Technological assessment of silicon on lattice engineered substrate (SOLES) for optical applications
MY Leung - 2008 - dspace.mit.edu
Over the past decade, much effort had been placed to integrate optoelectronic and
electronic devices. Silicon on lattice engineered substrate (SOLES) had been developed for …
electronic devices. Silicon on lattice engineered substrate (SOLES) had been developed for …
[引用][C] EFFECT OF CHANGE OF DIAMETER RATIO ON PERFORMANCE OF MWCNTS AS VLSI INTERCONNECTS
S Maheshwari, KSG Sandha - 2014