A wimedia/mboa-compliant cmos rf transceiver for uwb

C Sandner, S Derksen, D Draxelmayr… - IEEE Journal of Solid …, 2006 - ieeexplore.ieee.org
A WiMedia/MBOA compliant RF transceiver for ultra-wideband data communication in the 3-
5-GHz band is presented. The transceiver includes receiver, transmitter and synthesizer is …

Overview on ESD protection designs of low-parasitic capacitance for RF ICs in CMOS technologies

MD Ker, CY Lin, YW Hsiao - IEEE Transactions on Device and …, 2011 - ieeexplore.ieee.org
CMOS technology has been widely used to implement radio-frequency integrated circuits
(RF ICs). However, the thinner gate oxide in nanoscale CMOS technology seriously …

Transient behavior of SCRS during ESD pulses

K Esmark, H Gossner, S Bychikhin… - 2008 IEEE …, 2008 - ieeexplore.ieee.org
Silicon controlled rectifiers (SCRs) are widely used ESD protection elements exhibiting
extremely good voltage clamping and high failure current threshold. However, the turn-on …

[图书][B] ESD protection circuits for advanced CMOS technologies

JH Chun - 2006 - search.proquest.com
Electrostatic Discharge (ESD) has become one of the most critical reliability issues in
integrated circuits (ICs). In this dissertation, a variety of ESD issues in advanced …

ESD design strategies for high-speed digital and RF circuits in deeply scaled silicon technologies

S Cao, JH Chun, SG Beebe… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
Challenges of electrostatic discharge (ESD) protection in deeply scaled silicon technologies
are addressed by improving design, characterization, and modeling of I/O MOSFETs …

ESD-protected K-band low-noise amplifiers using RF junction varactors in 65-nm CMOS

MH Tsai, SSH Hsu, FL Hsueh… - IEEE transactions on …, 2011 - ieeexplore.ieee.org
This paper presents two K-band low-noise amplifiers (LNAs) in 65-nm CMOS using the
proposed RF junction varactors as the ESD protection devices. The junction varactors are …

Low-C ESD protection design with dual resistor-triggered SCRs in CMOS technology

CY Lin, CY Chen - IEEE Transactions on Device and Materials …, 2018 - ieeexplore.ieee.org
The electrostatic discharge (ESD) protection design with low parasitic capacitance seen at
I/O pad is needed for high-frequency applications. Conventional ESD protection designs …

ESD design challenges and strategies in deeply-scaled integrated circuits

S Cao, TW Chen, SG Beebe… - 2009 IEEE Custom …, 2009 - ieeexplore.ieee.org
Challenges of design window shrinkage in deeply scaled silicon technologies are
addressed by improving design, characterization, and modeling of I/O and ESD devices, and …

Nonlinear dynamics approach in modeling of the on-state-spreading-related voltage and current transients in 90nm CMOS silicon controlled rectifiers

D Pogany, D Johnsson, S Bychikhin… - 2009 IEEE …, 2009 - ieeexplore.ieee.org
Using a theory of front propagation in nonlinear active media we model the on-state
spreading related voltage, current and on-state width transients in 90 nm CMOS silicon …

3-D TCAD Methodology for Simulating Double-Hysteresis Filamentary IV Behavior and Holding Current in ESD Protection SCRs

H Karaca, S Holland, HM Ritter, V Kumar… - … on Electron Devices, 2021 - ieeexplore.ieee.org
Current filament (CF)-related double-hysteresis–behavior and holding current,, are analyzed
using experiments and 3-D technology computer-aided design (TCAD) simulation in silicon …