Implementation of error correction techniques in memory applications

N Sridevi, K Jamal, K Mannem - 2021 5th International …, 2021 - ieeexplore.ieee.org
As the technology scales down, various soft errors in SRAM memories occurs due to which
the single cell and multiple cell upsets are formed. Error correction codes such as the first …

Multiple adjacent bit error detection and correction codes for reliable memories: a review

K Neelima, C Subhas - … in Communications, Signal Processing, and VLSI …, 2021 - Springer
The memories and registers are the critical components in a processor which are prone to
errors like single bit upset or multiple bit upsets due to radiation effects. The error detection …

Ultrafast codes for multiple adjacent error correction and double error detection

LJ Saiz-Adalid, J Gracia-Moran, D Gil-Tomas… - IEEE …, 2019 - ieeexplore.ieee.org
Reliable computer systems employ error control codes (ECCs) to protect information from
errors. For example, memories are frequently protected using single error correction-double …

Lower complexity error location detection block of adjacent error correcting decoder for SRAMs

RK Maity, S Tripathi, J Samanta… - IET Computers & Digital …, 2020 - Wiley Online Library
Multiple cell upsets (MCUs) caused by radiation is an important issue related to the reliability
of embedded static random access memories (SRAMs). Multiple random and adjacent error …

Fast and power efficient sec-ded and sec-ded-daec codes in iot based wireless sensor networks

S Tripathi, J Jana, J Samanta… - TENCON 2019-2019 …, 2019 - ieeexplore.ieee.org
The internet of things (IoT) based wireless sensor networks (WSNs) have been employed in
many applications in industrial and medical fields. Smaller codeword length and low area …

Low overhead optimal parity codes

N Koppala, C Subhas - … Computing Electronics and Control), 2022 - telkomnika.uad.ac.id
The error detecting and correcting codes are used in critical applications like in intensive
care units, defense applications, and require highly reliable data. This brief focuses on …

Half diagonal matrix codes for reliable embedded memories

K Neelima, C Subhas - International journal of health sciences, 2022 - neliti.com
Reliability of embedded memories is dependent on at-speed rated correction capability of
error detection and correction codes. Many critical applications like medical databases …

FPGA based low area multi-bit adjacent error correcting codec for SRAM application

S Tripathi, RK Maity, J Jana, J Samanta… - Radioelectronics and …, 2020 - Springer
Mostly random and adjacent error correcting codes are used to protect stored data in
SRAMs against multiple bit upsets (MBUs). These MBUs caused by radiation are an …

Efficient adjacent 3D parity error detection and correction codes for embedded memories

K Neelima, C Subhas - 2020 IEEE International Conference on …, 2020 - ieeexplore.ieee.org
The detection and correction of errors during memory read operation performed per clock
cycle play a significant role in at-speed testing of embedded memories. The majority of key …

USING EXPERT EVALUATION FOR SELECTING AN ARCHITECTURAL SOLUTION FOR A SPECIALIZED SOFTWARE SYSTEM THAT MONITORS THE STATE OF …

V Sokolovskyi, E Zharikov… - … -European Journal of …, 2024 - search.ebscohost.com
The object of this study is the software and architectural solutions for specialized systems
that monitor the state of potentially hazardous facilities (hereinafter, PHF). The problem …