Successive Approximation Register Analog‐to‐Digital Converter (SAR ADC) for Biomedical Applications

KI Arafa, DM Ellaithy, A Zekry… - Active and Passive …, 2023 - Wiley Online Library
This study presents a survey of the most promising reported SAR ADC designs for
biomedical applications, stressing advantages, disadvantages, and limitations, and …

A 0.2-V 10-bit 5-kHz SAR ADC with dynamic bulk biasing and ultra-low-supply-voltage comparator

A Petrie, Y Song, W Kinnison, Y Qu… - … on Circuits and …, 2023 - ieeexplore.ieee.org
This paper describes a 10-bit 5-kHz SAR ADC under an ultra-low-supply-voltage of 0.2 V for
low-power applications. To tolerate the severe variations in the subthreshold regime, a novel …

A Reconfigurable 8-to-10-bit 20-to-5-GS/s time-interleaved time-domain ADC

J Wei, C Zhang, X Wang, Y Chang, M Liu - Microelectronics Journal, 2023 - Elsevier
This paper presents a 16-way time-interleaved (TI) time-domain (TD) analog-to-digital
converter (ADC) with full multiplexing of hardware resources and highly synchronous …

General approach to the calibration of innovative MFP multichannel digitizers

F Centurelli, P Monsurrò, A Trifiletti… - IEEE Transactions …, 2022 - ieeexplore.ieee.org
Innovative digitizers exploiting mixing, filtering, and processing (MFP) operations can grant
ultrahigh bandwidth and sampling rate. Their operation combines analog processing stages …

An Enhanced Photonic-Assisted Sampling Approach for Spectrum-Sparse Signal by Compressed Sensing

F Lyu, F Li, X Fang, N Zhang, X Ma - IEEE Access, 2022 - ieeexplore.ieee.org
Spectrum-sparse signals are vital for wideband radar and wireless communication
applications. A high-speed analog-to-digital converter (ADC) with the capacities of tens of …

A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

J Lan, D Zhai, Y Chen, Z Ni, X Shen, F Ye, J Ren - Electronics, 2021 - mdpi.com
A 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC is presented in 28-nm
CMOS. A bias-enhanced ring amplifier is utilized as the residue amplifier to achieve high …

A 2.72-fJ/Conversion-Step 13-bit SAR ADC With Wide Common-Mode Complementary Split Pre-Amplifier Comparator and Grounded-Finger CDAC

S Lee, H Kang, M Lee - IEEE Journal of Solid-State Circuits, 2024 - ieeexplore.ieee.org
This article presents a compact 13-bit 2-MS/s successive approximation register (SAR)
analog-to-digital converter (ADC) designed to enhance energy efficiency under various …

The sampling network for a 16-channel time-interleaved ADC

P Ji, C Liu, L Dang, S Li, R Ding, S Liu, Z Zhu - Microelectronics Journal, 2025 - Elsevier
This paper presents the design of a sampling network for an 8-bit, 16 GS/s, 16-channel time-
interleaved analog-to-digital converter (ADC) implemented in a 28 nm CMOS process. The …

A Subthreshold Time-Domain Analog Spiking Neuron With PLL-Based Leak Circuit and Capacitive DAC Synapse

T Barton, S Smith, Y Hao, R Watson… - IEEE Solid-State …, 2024 - ieeexplore.ieee.org
The design and measurement of a time-domain analog spiking neuron is described. The
proposed neuron leverages time-domain processing using voltage-controlled oscillators …

A configurable detection chip with±0.6% Inaccuracy for liquid conductivity using dual-frequency sinusoidal signal technique in 65 nm CMOS

Y Lin, Y Zhang, S Fu, H Zhang, P Wang - Microelectronics Journal, 2022 - Elsevier
This paper presents a configurable detection chip for liquid conductivity using a dual-
frequency sinusoidal signal technique. The proposed method improves the detection …