Monitoring performance of one or more architecturally sig nificant processor caches coupled
to a processor. The meth ods include executing an application on one or more proces sors …

The system and methods described herein may exploit hard ware transactional memory to
improve the performance of a Software or hybrid transactional memory implementation …

Systems and methods for optimizing code may use transac tional memory to optimize one
code section by forcing another code section to execute atomically. Application Source code …

According to one aspect, the Subject matter described herein includes a method for efficient
computer forensic analysis and data access control. The method includes steps occur ring …

Cache lines in a computing environment with transactional memory are configurable with a
coherency mode. Cachelines in full-line coherency mode are operated or managed with full …

A datapath circuit may include a digital multiply and accumulate circuit (MAC) and a digital
hardware calculator for parallel computation. The digital hardware calculator and the MAC …

6,636,949 B2 10/2003 Barroso et al. 6,925,537 B2 8, 2005 Barroso et al. 7,032,078 B2*
4/2006 Cypher et al................. 711 141 7,363,432 B2 4/2008 Gschwind et al. 7,475,193 B2 …

US8209499B2 - Method of read-set and write-set management by distinguishing between
shared and non-shared memory regions - Google Patents US8209499B2 - Method of read-set …

In one aspect, a method includes selecting a C-module; sending a write from a host to the
selected C-module; selecting a D-module to commit a page related to the write; selecting a …

In an embodiment of a transactional memory system, an apparatus includes a processor and
an execution logic to enable concurrent execution of at least one first software transaction of …