[HTML][HTML] Analytical Analysis of Power-Constrained Repeaters' Insertion in Large-Scale CMOS Chips

L Gaioni - Electronics, 2024 - mdpi.com
As the die area of CMOS integrated circuits continues to increase, interconnects will become
dominant in determining the performance of the circuits from the standpoint of speed and …

Agile Full-Chip Sign-Off in the Post-Moore Era

X Dong, S Sun, Z Chen, J Yang… - 2023 China …, 2023 - ieeexplore.ieee.org
Sign-off is a crucial step in the chip design flow to guarantee the performance and reliability
of chips prior to tape-out. However, the ever-growing integration density and voltage scaling …