Near-Data-Processing (NDP) architectures present a promising way to alleviate data
movement costs and can provide significant performance and energy benefits to parallel …

Increasing demand for power-efficient, high-performance computing has spurred a growing
number and diversity of hardware accelerators in mobile and server Systems on Chip …

Many future heterogeneous systems will integrate CPUs and GPUs physically on a single
chip and logically connect them via shared memory to avoid explicit data copying. Making …

While scalable coherence has been extensively studied in the context of general purpose
chip multiprocessors (CMPs), GPU architectures present a new set of challenges …

As the number of cores and threads in manycore compute accelerators such as Graphics
Processing Units (GPU) increases, so does the importance of on-chip interconnection …

Commodity heterogeneous systems (eg, integrated CPUs and GPUs), now support a
unified, shared memory address space for all components. Because the latency of global …

One of the most critical aspects of integrating loosely-coupled accelerators in
heterogeneous SoC architectures is orchestrating their interactions with the memory …

Recent work has shown that disciplined shared-memory programming models that provide
deterministic-by-default semantics can simplify both parallel software and hardware …

Architectural heterogeneity is increasing: numerous products and studies have proven the
benefits of combining cores and accelerators with varying ISAs into a single system …

We re-visit the issue of hardware consistency models in the new context of massively-
threaded throughput-oriented processors (MTTOPs). A prominent example of an MTTOP is a …