At-speed test has become a requirement in IC technologies below 180 nm. Unfortunately,
test mode switching activity and IR-drop present special challenges to the successful …

It is a well-known phenomenon that test power consumption may exceed that of functional
operation. ICs have been observed to fail at specified minimum operating voltages during …

The authors describe new strategies where at-speed scan tests can be applied with internal
PLL. They present techniques for optimizing ATPG across multiple clock domains and …

With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be
checked for newer defects. While scan-based architectures help detect these defects using …

To detect the smallest delay faults at a fault site, the longest path (s) through it must be tested
at full speed. Existing test generation tools are inefficient in automatically identifying the …

Due to shrinking technology, increasing functional frequency and density, and reduced
noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise …

This paper presents delay test data collected from test chips fabricated in a 0.18/spl
mu/technology. The experimental data shows that process monitor structures such as on …

Faster-than-at-speed test have been proposed to detect small delay defects. While these
techniques increase the test frequency to reduce the positive slack of the path, they …

A novel scan-based delay test approach, referred as the hybrid delay scan, is proposed in
this paper. The proposed scan-based delay testing method combines advantages of the …

The sensitivity of very deep submicron designs to supply voltage noise is increasing due to
higher path delay variations and reduced noise margins with supply noise scaling. The …