[图书][B] VLSI test principles and architectures: design for testability

LT Wang, CW Wu, X Wen - 2006 - books.google.com
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …

Embedded deterministic test

J Rajski, J Tyszer, M Kassab… - IEEE transactions on …, 2004 - ieeexplore.ieee.org
This paper presents a novel test-data volume-compression methodology called the
embedded deterministic test (EDT), which reduces manufacturing test cost by providing one …

Survey of test vector compression techniques

NA Touba - IEEE Design & test of computers, 2006 - ieeexplore.ieee.org
Test data compression consists of test vector compression on the input side and response,
compaction on the output side. This vector compression has been an active area of …

[图书][B] System-on-chip test architectures: nanometer design for testability

LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …

Extending relational database systems to automatically enforce privacy policies

R Agrawal, P Bird, T Grandison… - … Conference on Data …, 2005 - ieeexplore.ieee.org
Databases are at the core of successful businesses. Due to the voluminous stores of
personal data being held by companies today, preserving privacy has become a crucial …

Optimal selective Huffman coding for test-data compression

X Kavousianos, E Kalligeros… - IEEE transactions on …, 2007 - ieeexplore.ieee.org
Selective Huffman coding has recently been proposed for efficient test-data compression
with low hardware overhead. In this paper, we show that the already proposed encoding …

[HTML][HTML] A Review of Test Stimulus Compression Methods for Ultra-Large-Scale Integrated Circuits

L Zhou, D Yang, L Chen, W Zhuang, S Zhang… - Applied Sciences, 2024 - mdpi.com
With the development of system-on-chip (SoC) and chiplet technology in the post-Moore era,
an increasing number of chiplets are being integrated into a single chip. Consequently, the …

Test data compression for IP embedded cores using selective encoding of scan slices

Z Wang, K Chakrabarty - IEEE International Conference on Test …, 2005 - ieeexplore.ieee.org
We present a selective encoding method that reduces test data volume and test application
time for scan testing of intellectual property (IP) cores. This method encodes the slices of test …

Test set embedding for deterministic BIST using a reconfigurable interconnection network

L Li, K Chakrabarty - … Transactions on computer-aided design of …, 2004 - ieeexplore.ieee.org
We present a new approach for deterministic built-in self-test (BIST) in which a
reconfigurable interconnection network (RIN) is placed between the outputs of a …

Low-power programmable PRPG with test compression capabilities

M Filipek, G Mrugalski, N Mukherjee… - … Transactions on Very …, 2014 - ieeexplore.ieee.org
This paper describes a low-power (LP) programmable generator capable of producing
pseudorandom test patterns with desired toggling levels and enhanced fault coverage …