With the advent of portable and high-density microelectronic devices, the power dissipation
of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and …

Reduction of power dissipation during test application is studied for scan designs and for
combinational circuits tested using built-in self-test (BIST). The problems are shown to be …

In this paper, we consider the problem of calculating the signal and transition probabilities of
the internal nodes of the combinational logic part of a nite state machine (FSM). Giv en the …

With the advent of portable and high-density microelectronic devices, the power dissipation
of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and …

This paper describes various approaches for power analysis and minimization at the logic
level including, amongst others, pattern-independent probabilistic and symbolic simulation …

We demonstrate a new approach minimizing the total ofthe static and the dynamic power
dissipation components in aCMOS logic network required to operate at a specified …

In this paper, a new approach is presented for estimating the hot-carrier induced
degradation in MOS transistors in VLSI circuits. With the decrease in feature size, many long …

With the shift to low power IC design for personal computing and communication
applications, designers' priorities turn to accurate and efficient estimation of power …

We present a profiling based technique for power estimation. This technique is implemented
in the PDSS (Profile Driven Synthesis System) for the synthesis of low power designs …

In this paper, we propose a timing dependent dynamic power estimation framework that
considers the impact of coupling and glitches. We show that relative switching activities and …