One of the most critical challenges for today's and future data-intensive and big-data
problems is data storage and analysis. This paper first highlights some challenges of the …

Wristbands have been traditionally designed to track the activities of a single person.
However there is an opportunity to utilize the sensing capabilities of wristbands to offer …

Many studies focus on implementing processing-in memory (PIM) on the logic die of the
hybrid memory cube (HMC) architecture. The multiply-accumulate (MAC) operation is …

Each memory device presented has its unique range of advantages and challenges. DRAM
and FLASH have radically different characteristics; hence, they are used for different …

Today's computing systems suffer from memory/communication bottleneck, resulting in
energy and performance inefficiency. This makes them incapable to solve data-intensive …

Abstract Tiled Dynamic Adaptive Neural Network Array (Tiled DANNA) is a recurrent spiking
neural network structure composed of programmable biologically inspired neurons and …

The MIP SCOC was designed to overcome the Von-Neumann bottleneck and develop
massive on-chip parallelism to achieve Teraflop scale single chip performance. We case …

The Von Neumann Architecture Topic Paper #3 Page 1 The Von Neumann Architecture Topic
Paper #3 Alex Laird CS-3210-01 1/21/09 Survey of Programming Languages Spring 2009 …

As a result of the increasing requirements of present and future computation intensive
applications, there have been many fundamentally divergent approaches such as the Blue …

Partitioned Parallel Processing Approach for Predicting Multi-Million Neuron
Interconnectivity in the Brain : Involving Soma-Axo Page 1 Partitioned Parallel Processing …