Trending IC design directions in 2022
For the non-stop demands for a better and smarter society, the number of electronic devices
keeps increasing exponentially; and the computation power, communication data rate, smart …
keeps increasing exponentially; and the computation power, communication data rate, smart …
A 20-GHz PLL with 20.9-fs random jitter
Y Zhao, M Forghani, B Razavi - IEEE Journal of Solid-State …, 2022 - ieeexplore.ieee.org
This article describes an integer-phase-locked loop (PLL) that incorporates a phase detector
sampling both the rising and falling edges of the reference clock. The circuit also uses a new …
sampling both the rising and falling edges of the reference clock. The circuit also uses a new …
Multirate timestamp modeling for ultralow-jitter frequency synthesis: A tutorial
Y Hu, T Siriburanon… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this tutorial brief, we introduce a unified wideband phase-noise theory framework of
frequency synthesis based on a multirate timestamp modeling with “two-variables”. We …
frequency synthesis based on a multirate timestamp modeling with “two-variables”. We …
A 30-GHz class-F quadrature DCO using phase shifts between drain–gate–source for low flicker phase noise and I/Q exactness
In this article, we present a low phase noise (PN) mm-wave quadrature digitally controlled
oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A …
oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A …
A Fully Integrated QPSK/16-QAM -Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces
This work presents a fully integrated D-band transceiver (TRX) in 28-nm CMOS. The system
architecture introduces a radio-frequency digital-to-analog converter (RF-DAC) and the …
architecture introduces a radio-frequency digital-to-analog converter (RF-DAC) and the …
A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary–Secondary S-PD Measuring 39.6-fsRMS Jitter, −260.2-dB FOM, and −70.96–dBc …
This paper reports an active-buffer-free type-I sampling phase-locked loop (S-PLL). We
innovate a fully-passive sampling phase detector with passive-gain multiplication after the …
innovate a fully-passive sampling phase detector with passive-gain multiplication after the …
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter, −258.7-dB FOM, and −75.17-dBc Reference Spur
This article presents a low-jitter and low-spur type-II sampling phase-locked loop (S-PLL).
The innovative introduction of a differential parallel-series double-edge sampling phase …
The innovative introduction of a differential parallel-series double-edge sampling phase …
A 25.8-GHz integer-N CPPLL achieving 60-fs rms jitter and robust lock acquisition based on a time–amplifying phase–frequency detector
This article presents a 25.8-GHz integer-N charge pump phase-locked loop (CPPLL). With
the proposed time–amplifying phase–frequency detector (TAPFD), the in-band noise is …
the proposed time–amplifying phase–frequency detector (TAPFD), the in-band noise is …
A Compact 20–24-GHz Sub-Sampling PLL With Charge-Domain Bandwidth Control Scheme
This article introduces a compact 20–24-GHz integer-dual-path sub-sampling phase-locked
loop (DPSSPLL) with a charge-domain bandwidth control scheme. By leveraging the …
loop (DPSSPLL) with a charge-domain bandwidth control scheme. By leveraging the …
A Low-Noise Digital-to-Time Converter Exploiting Waveform of Integrated Crystal Oscillator
T Siriburanon, X Chen, C Liu, J Du… - IEEE Journal of Solid …, 2024 - ieeexplore.ieee.org
In this article, we propose a digital-to-time conversion technique operating entirely in the
sinusoidal waveform voltage domain of a crystal oscillator (XO) before the signal's final …
sinusoidal waveform voltage domain of a crystal oscillator (XO) before the signal's final …