Efficient and deadlock-free routing is critical to the performance of networks-on-chip. The
effectiveness of any adaptive routing algorithm strongly depends on the underlying selection …

This tutorial presents the details of the interconnection network utilized in many high
performance computing (HPC) systems today.“InfiniBand” is the hardware interconnect …

In this paper we present a methodology to develop efficient and deadlock free routing
algorithms for Network-on-Chip (NoC) platforms which are specialized for an application or …

Aggressive transistor scaling continues to drive increasingly complex digital designs. The
large number of transistors available today enables the development of chip multiprocessors …

Computers get faster every year, but the demand for computing resources seems to grow at
an even faster rate. Depending on the problem domain, this demand for more power can be …

Extreme transistor technology scaling is causing increasing concerns in device reliability:
the expected lifetime of individual transistors in complex chips is quickly decreasing, and the …

Traditional architectural designs are normally focused on CPUs and have been often
decoupled from I/O considerations. They are inefficient for high-speed network processing …

Many cut-through switches, which can greatly reduce network latency, are commercially
available for the construction of high-speed local area networks. The interconnection of cut …

Networks of workstations (NOWs) are being considered as a cost-effective alternative to
parallel computers. Many NOWs are arranged as a switch-based network with irregular …

Networks of workstations (NOWs) are being considered as a cost-effective alternative to
parallel computers. Most NOWs are arranged as a switch-based network and provide …