Semeru: A {Memory-Disaggregated} managed runtime

C Wang, H Ma, S Liu, Y Li, Z Ruan, K Nguyen… - … USENIX Symposium on …, 2020 - usenix.org
Resource-disaggregated architectures have risen in popularity for large datacenters.
However, prior disaggregation systems are designed for native applications; in addition, all …

Recent advances in computer architecture: The opportunities and challenges for provenance

N Balakrishnan, T Bytheway, L Carata… - 7th USENIX Workshop …, 2015 - usenix.org
In recent years several hardware and systems fields have made advances in technology that
open new opportunities and challenges for provenance systems. In this paper we look at …

Semantics-Guided Systems Foundations for Disaggregated Datacenters

H Ma - 2024 - escholarship.org
Resource disaggregation has emerged as a promising solution to enhance both resource
utilization and management efficiency in datacenters. Existing disaggregation solutions …

Programmable fpga-based memory controller

S Wijeratne, S Pattnaik, Z Chen… - … IEEE Symposium on …, 2021 - ieeexplore.ieee.org
Even with generational improvements in DRAM technology, memory access latency still
remains the major bottleneck for application accelerators, primarily due to limitations in …

A survey on attack vectors in stack cache memory

N Khoshavi, M Maghsoudloo, Y Bi, W Francois… - Integration, 2020 - Elsevier
Over past few decades, various ways have been conducted through side channel attacks to
steal information for a computer system. Unlike conventional hardware-based methods, ie …

Semeru: A memory-disaggregated managed runtime

HM Chenxi Wang, MIT Zhenyuan Ruan… - … USENIX Symposium on …, 2020 - par.nsf.gov
Resource-disaggregated architectures have risen in popularity for large datacenters.
However, prior disaggregation systems are designed for native applications; in addition, all …

Processor with memory controller including dynamically programmable functional unit

GG Henry, RE Hooker, T Parks, DR Reed - US Patent 11,061,853, 2021 - Google Patents
A processor including a memory controller for interfacing an external memory and a
programmable functional unit (PFU). The PFU is programmed by a PFU program to modify …

Power-Efficient Instancy Aware DRAM Scheduling

GY Pan, CY Lai, JY Jou, BCC Lai - IEICE Transactions on …, 2015 - search.ieice.org
Nowadays, computer systems are limited by the power and memory wall. As the Dynamic
Random Access Memory (DRAM) has dominated the power consumption in modern …

[PDF][PDF] A Complete Bibliography of ACM Transactions on Computer Systems

NHF Beebe - 2024 - netlib.org
A Complete Bibliography of ACM Transactions on Computer Systems Page 1 A Complete
Bibliography of ACM Transactions on Computer Systems Nelson HF Beebe University of …

[引用][C] Statement of Research Interests