Memristor based computation-in-memory architecture for data-intensive applications
S Hamdioui, L Xie, HA Du Nguyen… - … , Automation & Test …, 2015 - ieeexplore.ieee.org
One of the most critical challenges for today's and future data-intensive and big-data
problems is data storage and analysis. This paper first highlights some challenges of the …
problems is data storage and analysis. This paper first highlights some challenges of the …
[图书][B] On-chip communication architectures: system on chip interconnect
S Pasricha, N Dutt - 2010 - books.google.com
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …
increasing complexity of applications, fueled by the era of digital convergence …
A latent topic model for complete entity resolution
In bibliographies like DBLP and Citeseer, there are three kinds of entity-name problems that
need to be solved. First, multiple entities share one name, which is called the name sharing …
need to be solved. First, multiple entities share one name, which is called the name sharing …
Power emulation: a new paradigm for power estimation
J Coburn, S Ravi, A Raghunathan - Proceedings of the 42nd Annual …, 2005 - dl.acm.org
In this work, we propose a new paradigm called power emulation, which exploits hardware
acceleration to drastically speedup power estimation. Power emulation is based on the …
acceleration to drastically speedup power estimation. Power emulation is based on the …
PowerViP: Soc power estimation framework at transaction level
In this work, we propose a SoC power estimation framework built on our system-level
simulation environment. Our framework provides designers with the system-level power …
simulation environment. Our framework provides designers with the system-level power …
On the implementation of computation-in-memory parallel adder
Today's computer architectures suffer from many challenges, such as the near end of CMOS
downscaling, the memory/communication bottleneck, the power wall, and the programming …
downscaling, the memory/communication bottleneck, the power wall, and the programming …
[图书][B] Network-on-chip architectures: A holistic design exploration
[2]. The Cell Processor from Sony, Toshiba and IBM (STI)[3], and the Sun UltraSPARC T1
(formerly codenamed Niagara)[4] signal the growing popularity of such systems …
(formerly codenamed Niagara)[4] signal the growing popularity of such systems …
System-wide leakage-aware energy minimization using dynamic voltage scaling and cache reconfiguration in multitasking systems
System optimization techniques are widely used to improve energy efficiency as well as
overall performance. Dynamic voltage scaling (DVS) is well studied and known to be …
overall performance. Dynamic voltage scaling (DVS) is well studied and known to be …
Power modeling and characterization of computing devices
In this survey we describe the main research directions in pre-silicon power modeling and
post-silicon power characterization. We review techniques in power modeling and …
post-silicon power characterization. We review techniques in power modeling and …
NoCEE: energy macro-model extraction methodology for network on chip routers
J Chan, S Parameswaran - ICCAD-2005. IEEE/ACM …, 2005 - ieeexplore.ieee.org
In this paper we present NoCEE, a fast and accurate method for extracting energy models
for packet-switched network on chip (NoC) routers. Linear regression is used to model the …
for packet-switched network on chip (NoC) routers. Linear regression is used to model the …