S Vidhyadharan, SS Dan - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This paper presents a novel ultra-low power yet high-performance device and circuit design paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs …
This paper investigates a method to suppress the ambipolar current I amb effectively, enhance the device performance with higher on current I on, lower off current I off, lower …
In this article, for the first time, an asymmetric U-shaped-gated tunnel FET (AU-TFET), with a unique vertical channel epilayer, at sub-7-nm technology node, has been proposed and …
S Vidhyadharan, SS Dan, R Yadav… - International Journal of …, 2020 - Taylor & Francis
Recent researches have indicated that the gate-overlap tunnel FETs (GOTFETs) exhibit double the on-currents I on and one-tenth the off-currents I off than the equally sized …
This paper presents a highly efficient ternary flash ADC, designed using the innovative gate- overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have …
In this work, we propose and investigate a new pocket‐based Si0. 55Ge0. 45/Si gate normal tunnel FET design employing a gate over source with a single lateral pocket (GSLP) with …
This paper introduces an innovative Gate-Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield around double the on current I on, while the off current I …
Energy saving is a most promising sector of research and development. Nowadays, energy saving or low power is becoming a critical challenge that is most important for the future of …
H Simhadri, SS Dan, R Yadav… - International Journal of …, 2021 - Wiley Online Library
This paper presents a double‐gate line‐tunneling field‐effect transistor (DGLTFET) device optimized for superior analog performance. DGLTFET has thrice the on currents I on, at least …