A modern primer on processing in memory
Modern computing systems are overwhelmingly designed to move data to computation. This
design choice goes directly against at least three key trends in computing that cause …
design choice goes directly against at least three key trends in computing that cause …
DAMOV: A new methodology and benchmark suite for evaluating data movement bottlenecks
Data movement between the CPU and main memory is a first-order obstacle against improv
ing performance, scalability, and energy efficiency in modern systems. Computer systems …
ing performance, scalability, and energy efficiency in modern systems. Computer systems …
A deeper look into rowhammer's sensitivities: Experimental analysis of real dram chips and implications on future attacks and defenses
RowHammer is a circuit-level DRAM vulnerability where repeatedly accessing (ie,
hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer …
hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer …
QUAC-TRNG: High-throughput true random number generation using quadruple row activation in commodity DRAM chips
True random number generators (TRNG) sample random physical processes to create large
amounts of random numbers for various use cases, including security-critical cryptographic …
amounts of random numbers for various use cases, including security-critical cryptographic …
Benchmarking memory-centric computing systems: Analysis of real processing-in-memory hardware
Many modern workloads such as neural network inference and graph processing are
fundamentally memory-bound. For such workloads, data movement between memory and …
fundamentally memory-bound. For such workloads, data movement between memory and …
HiRA: Hidden row activation for reducing refresh latency of off-the-shelf DRAM chips
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …
periodically refreshed to prevent data loss. Refresh operations degrade system performance …
Towards efficient sparse matrix vector multiplication on real processing-in-memory architectures
Several manufacturers have already started to commercialize near-bank Processing-In-
Memory (PIM) architectures, after decades of research efforts. Near-bank PIM architectures …
Memory (PIM) architectures, after decades of research efforts. Near-bank PIM architectures …
DRAM bender: An extensible and versatile FPGA-based infrastructure to easily test state-of-the-art DRAM chips
To understand and improve DRAM performance, reliability, security, and energy efficiency,
prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art …
prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art …
PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM
Commodity DRAM-based processing-using-memory (PuM) techniques that are supported
by off-the-shelf DRAM chips present an opportunity for alleviating the data movement …
by off-the-shelf DRAM chips present an opportunity for alleviating the data movement …
MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data …
Processing-using-DRAM (PUD) is a processing-in-memory (PIM) approach that uses a
DRAM array's massive internal parallelism to execute very-wide (eg, 16,384-262,144-bit …
DRAM array's massive internal parallelism to execute very-wide (eg, 16,384-262,144-bit …