Energy-efficient time-based adaptive encoding for off-chip communication

E Maragkoudaki, VF Pavlidis - IEEE Transactions on Very Large …, 2020 - ieeexplore.ieee.org
The energy for data transfer has an increasing effect on the total system energy as
technology scales, often overtaking computation energy. To reduce the power of interchip …

An algorithm-hardware co-design framework to overcome imperfections of mixed-signal dnn accelerators

P Behnam, U Kamal, S Mukhopadhyay - arXiv preprint arXiv:2208.13896, 2022 - arxiv.org
In recent years, processing in memory (PIM) based mixedsignal designs have been
proposed as energy-and area-efficient solutions with ultra high throughput to accelerate …

STFL-DDR: Improving the energy-efficiency of memory interface

P Behnam, MN Bojnordi - IEEE Transactions on Computers, 2020 - ieeexplore.ieee.org
Power dissipation is a significant problem limiting the performance of today's computer
systems. One of the main contributors to power consumption in microprocessors is data …

RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC

A Sarman, A Shaju, RG Kunthara… - 2022 IFIP/IEEE 30th …, 2022 - ieeexplore.ieee.org
In modern Tiled Chip Multicore Processor (TCMP) systems, Network on Chip (NoC) is the
preferred interconnect solution to overcome scalability and performance bottleneck issues …

Signature codes for energy-efficient data movement in on-chip networks

M Dehyadegari - Journal of Computing and Security, 2020 - jcomsec.ui.ac.ir
On-chip networks provide a scalable infrastructure for moving data among cores in many-
core systems. In future technologies, significant amounts of dynamic energy are dissipated …

Multiwire phase encoding: A signaling strategy for high-bandwidth, low-power data movement

P Mukim, F Brewer - IEEE Transactions on Very Large Scale …, 2021 - ieeexplore.ieee.org
This article presents multiwire phase encoding (MWPE), a transition signaling technique
aimed at chip-to-chip communication on silicon interposer technology, where multiple …

[图书][B] Energy Efficient Encoding Methods for Chip-To-Chip Communication

E Maragkoudaki - 2022 - search.proquest.com
As traditional scaling slows down, the number of cores and the amount of memory per
system increase to satisfy the performance demand. This drive for more parallelism …

Reliable Power Efficient Systems through Run-time Reconfiguration

N El-Araby, A Jantsch - 2022 20th IEEE Interregional NEWCAS …, 2022 - ieeexplore.ieee.org
We propose a methodology for optimizing the reliability, power, area, and performance of
Field Programmable Gate Array (FPGA)-based systems at run time based on dynamic …

Buffer allocation for reducing block transit penalty

KK Muchherla, P Feeley, J Zhu, F Zhu, A Goda… - US Patent …, 2024 - Google Patents
Methods, systems, and apparatuses include receiving a write command including user data.
The write command is directed to a portion of memory including a first block and a second …