Low-precision arithmetic operations to accelerate deep-learning applications on field-
programmable gate arrays (FPGAs) have been studied extensively, because they offer the …

As silicon technology advances, field programmable gate arrays appear to gain ground
against the traditional ASIC project starts, reaching out to form the mainstream …

This paper introduces a new heuristic to generate pipelined run-time reconfigurable
constant multipliers for field-programmable gate arrays (FPGAs). It produces results close to …

This paper presents a new method called optimal shift reassignment (OSR), used for
reconfigurable multiplication circuits. These circuits consist of adders, subtractors, shifts, and …

This paper presents a new algorithm to automatically create pipelined run-time
reconfigurable constant multipliers. Reconfiguration between several constants is achieved …

This book addresses the question how run-time reconfigurable constant multipliers (RCMs)
can be efficiently implemented on field programmable gate arrays (FPGAs). RCMs calculate …

Abstract In recent years, Deep Neural Networks (DNNs) become an area of high interest due
to it's ground-breaking results in many fields and applications. In many of these applications …

This paper proposes a capable constant multiplier architecture with the help of an
architecture called Binary Common Sub-Expression (BCSE) algorithm. As multiplication …

This article introduces a new heuristic to generate pipelined run-time reconfigurable
constant multipliers for field programmable gate arrays (FPGAs). It produces results close to …