A Triple Burst Error Correction Based on Region Selection Code

F Silva, AC Pinheiro, JAN Silveira… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
The evolution of microelectronics boosts more scalable and complex circuit designs,
providing high processing speed and greater storage capacity. However, reliability issues …

An efficient EDAC approach for handling multiple bit upsets in memory array

RC Goerl, PRC Villa, LB Poehls, EA Bezerra… - Microelectronics …, 2018 - Elsevier
Ionizing radiation and electromagnetic interference (EMI) can cause single event upset
(SEU) in memory elements. This threat is one of the major concerns when considering the …

An extensible code for correcting multiple cell upset in memory arrays

F Silva, J Silveira, J Silveira, C Marcon… - Journal of Electronic …, 2018 - Springer
As the microelectronics technology continuously advances to deep submicron scales, the
occurrence of Multiple Cell Upset (MCU) induced by radiation in memory devices becomes …

CLC-A: An adaptive implementation of the Column Line Code (CLC) ECC

F Silva, A Muniz, J Silveira… - 2020 33rd Symposium on …, 2020 - ieeexplore.ieee.org
Column-Line-Code (CLC) is an Error Correction Code (ECC) designed to correct multiple
errors in memory devices for critical applications. CLC has originally two decoder modes …

Extended matrix region selection code: An ECC for adjacent multiple cell upset in memory arrays

F Silva, W Freitas, J Silveira, C Marcon… - Microelectronics …, 2020 - Elsevier
With the widespread of electronics nowadays, Single Event Effects (SEEs) have become a
significant concern, not only for critical applications like aerospace and military but also for …

An efficient, low-cost ECC approach for critical-application memories

F Silva, O Lima, W Freitas, F Vargas, J Silveira… - Proceedings of the 30th …, 2017 - dl.acm.org
Multiple Cell Upsets (MCUs) induced by ionizing radiation in memories are becoming more
likely to happen due to the continuous technology scaling down. Error Correction Codes …

READ: Reliability enhancement in 3D-Memory exploiting asymmetric SER distribution

H Han, J Chung, JS Yang - IEEE Transactions on Computers, 2018 - ieeexplore.ieee.org
3D-memory is one of promising applications in 3D-IC technology. With a 3D integration
technology, the effective density of memories can increase and the interconnect distance …

Efficient implementation of error correction codes in hash tables

P Reviriego, S Pontarelli, JA Maestro, M Ottavi - Microelectronics Reliability, 2014 - Elsevier
Hash tables are one of the most commonly used data structures in computing applications.
They are used for example to organize a data set such that searches can be performed …

Exploiting unused spare columns and replaced columns to enhance memory ECC

H Han, NA Touba, JS Yang - IEEE Transactions on Computer …, 2017 - ieeexplore.ieee.org
Due to the emergence of extremely high density memory along with the growing number of
embedded memories, memory yield is an important issue. Memory self-repair using …

Asymmetric ECC organization in 3D-memory via spare column utilization

H Han, JS Yang - … IEEE International Symposium on Defect and …, 2015 - ieeexplore.ieee.org
3D-memory and processor-memory structures are promising applications of 3D-IC
technology. With 3D integration, the effective density of memories can increase and the …