This newly revised and expanded edition of the 2003 Artech House classic, Radio Frequency Integrated Circuit Design, serves as an up-to-date, practical reference for …
HR Rategh, TH Lee - IEEE Journal of Solid-State Circuits, 1999 - ieeexplore.ieee.org
Injection-locked oscillators (ILOs) are investigated in a new theoretical approach. A first- order differential equation is derived for the noise dynamics of ILOs. A single-ended injection …
A new and innovative paradigm for RF frequency synthesis and wireless transmitter design Learn the techniques for designing and implementing an all-digital RF frequency …
A general model of phase-locked loops (PLLs) is derived which incorporates the influence of divide value variations. The proposed model allows straightforward noise and dynamic …
This tutorial paper examines architectural and circuit design techniques for a microsensor node operating at power levels low enough to enable the use of an energy harvesting …
S Pamarti, L Jansson, I Galton - IEEE Journal of Solid-State …, 2004 - ieeexplore.ieee.org
A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, are presented and demonstrated as enabling …
PE Su, S Pamarti - IEEE Transactions on Circuits and Systems …, 2009 - ieeexplore.ieee.org
The fundamentals and state of the art in fractional-N phase-locked-loop (PLL)-based frequency synthesis are reviewed. Particular emphasis is placed on delta-sigma fractional-N …
S Ye, L Jansson, I Galton - IEEE Journal of Solid-State Circuits, 2002 - ieeexplore.ieee.org
An enhancement to a conventional integer-N phase-locked loop (PLL) is introduced, analyzed, and demonstrated experimentally to significantly reduce voltage-controlled …
HR Rategh, H Samavati, TH Lee - IEEE Journal of Solid-State …, 2000 - ieeexplore.ieee.org
A fully integrated 5-GHz phase-locked loop (PLL) based frequency synthesizer is designed in a 0.24/spl mu/m CMOS technology. The power consumption of the synthesizer is …