All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

RB Staszewski, K Muhammad… - IEEE Journal of Solid …, 2004 - ieeexplore.ieee.org
We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm
CMOS process. The transceiver is architectured from the ground up to be compatible with …

[图书][B] Radio frequency integrated circuit design

JWM Rogers, C Plett - 2010 - books.google.com
This newly revised and expanded edition of the 2003 Artech House classic, Radio
Frequency Integrated Circuit Design, serves as an up-to-date, practical reference for …

Superharmonic injection-locked frequency dividers

HR Rategh, TH Lee - IEEE Journal of Solid-State Circuits, 1999 - ieeexplore.ieee.org
Injection-locked oscillators (ILOs) are investigated in a new theoretical approach. A first-
order differential equation is derived for the noise dynamics of ILOs. A single-ended injection …

[图书][B] All-digital frequency synthesizer in deep-submicron CMOS

RB Staszewski, PT Balsara - 2006 - books.google.com
A new and innovative paradigm for RF frequency synthesis and wireless transmitter design
Learn the techniques for designing and implementing an all-digital RF frequency …

A modeling approach for/spl Sigma/-/spl Delta/fractional-N frequency synthesizers allowing straightforward noise analysis

MH Perrott, MD Trott, CG Sodini - IEEE Journal of Solid-State …, 2002 - ieeexplore.ieee.org
A general model of phase-locked loops (PLLs) is derived which incorporates the influence of
divide value variations. The proposed model allows straightforward noise and dynamic …

Design considerations for ultra-low energy wireless microsensor nodes

BH Calhoun, DC Daly, N Verma… - IEEE Transactions …, 2005 - ieeexplore.ieee.org
This tutorial paper examines architectural and circuit design techniques for a microsensor
node operating at power levels low enough to enable the use of an energy harvesting …

A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation

S Pamarti, L Jansson, I Galton - IEEE Journal of Solid-State …, 2004 - ieeexplore.ieee.org
A phase noise cancellation technique and a charge pump linearization technique, both of
which are insensitive to component errors, are presented and demonstrated as enabling …

Fractional- Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial

PE Su, S Pamarti - IEEE Transactions on Circuits and Systems …, 2009 - ieeexplore.ieee.org
The fundamentals and state of the art in fractional-N phase-locked-loop (PLL)-based
frequency synthesis are reviewed. Particular emphasis is placed on delta-sigma fractional-N …

A multiple-crystal interface PLL with VCO realignment to reduce phase noise

S Ye, L Jansson, I Galton - IEEE Journal of Solid-State Circuits, 2002 - ieeexplore.ieee.org
An enhancement to a conventional integer-N phase-locked loop (PLL) is introduced,
analyzed, and demonstrated experimentally to significantly reduce voltage-controlled …

A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver

HR Rategh, H Samavati, TH Lee - IEEE Journal of Solid-State …, 2000 - ieeexplore.ieee.org
A fully integrated 5-GHz phase-locked loop (PLL) based frequency synthesizer is designed
in a 0.24/spl mu/m CMOS technology. The power consumption of the synthesizer is …