Robust Random Number Generators (RNGs) are indispensable components in modern
cryptographic systems, secure communications, and various other applications where …

The use of highly iterative software development methodologies, such as Agile and Lean,
have been growing. However, these methodologies do not explicitly provide practices for …

An effective logic built-in self-test scheme aiming at reducing the area overhead of IC testing
and improving the fault average is proposed, which combines strategies of linear feedback …

A new built-in-self-test scheme, referred to as Test Vectors Applied by Circuit-under-Test
(TVAC), is proposed in this paper. As the point of view of the paper, Circuit-under-Test (CUT) …

The seed (initial state) of a pseudo-random pattern generator (PRPG) for built-in self-test
(BIST), significantly influences the fault coverage and total test application time. This paper …

In this paper, we discuss the application of a seed-selection procedure for LFSR-based BIST
to multiple scan chains, combined with a phase shifter. We introduced the procedures for …

This paper gives an overview of on chip testing method. The test pattern generator
generates appropriate test patterns that provide a highest possible fault coverage. The goal …

In this paper, a fast seed selection implementation procedure for LFSR based
pseudorandom pattern generation in hybrid technique is described. This selection technique …

THE PRIMARY CHALLENGE during the modern integrated circuit development process lies
in coping with the progressively shorter time-to-market of the chips. Modular design through …

In this paper, we analyze the distribution of fault coverage in random-pattern testing. While
our discussion here overlaps in part with several previous works, some new aspects for the …