The recently introduced model checking algorithm, IC3, has proved to be among the best
SAT-based safety model checkers. Many implementations now exist. This paper provides …

Recent research results have shown that the traditional structural testing for delay and
crosstalk faults may result in over-testing due to the non-trivial number of such faults that are …

In recent years SAT solving has been widely used to implement various circuit
transformations in logic synthesis. However, off-the-shelf CNF-based SAT solvers often have …

Finding the cause of a bug can be one of the most time-consuming activities in design
verification. This is particularly true in the case of bugs discovered in the context of a random …

In this paper, we propose an integrated approach that combines a circuit-based SAT solver
(CirSAT) with a technique based on XOR-Majority Graph (XMG) rewriting for logic …

Many CAD for VLSI techniques use time-frame expansion, also known as the Iterative Logic
Array representation, to model the sequential behavior of a system. Replicating industrial …

Recent research results have shown that the traditional structural testing for delay and signal
integrity faults may result in overtesting due to the nontrivial number of such faults that are …

In this paper, we propose two fault-diagnosis methods for improving multiple-fault diagnosis
resolution. The first method, based on the principle of single-fault activation and single …

The paper addresses a key aspect of efficient computation in logic synthesis and formal
verification, namely, the integration of a circuit simulator and a Boolean satisfiability solver. A …

We propose a novel methodology for design error diagnosis in the HDL description using a
word-level solver. In this approach, the patterns that result in erroneous responses are first …