[PDF][PDF] Review on non-linear set associative cache design

E Malathy, CS Thirumalai - IJPT, 2016 - researchgate.net
In the modern world, computer system plays a vital role based on type of applications.
Hence, there is a need to research and develop such system to improve its performance. In …

Exploring the energy-latency trade-off for broadcasts in energy-saving sensor networks

MJ Miller, C Sengul, I Gupta - 25th IEEE International …, 2005 - ieeexplore.ieee.org
Networking protocols for multi-hop wireless sensor networks (WSNs) are required to
simultaneously minimize resource usage as well as optimize performance metrics such as …

Acic: Admission-controlled instruction cache

Y Wang, CH Chang… - … Symposium on High …, 2023 - ieeexplore.ieee.org
The front end bottleneck in datacenter workloads has come under increased scrutiny, with
the growing code footprint, involvement of numerous libraries and OS services, and the …

An intelligent cache system with hardware prefetching for high performance

JH Lee, S Jeong, SD Kim… - IEEE Transactions on …, 2003 - ieeexplore.ieee.org
We present a high performance cache structure with a hardware prefetching mechanism that
enhances exploitation of spatial and temporal locality. The proposed cache, which we call a …

Energy efficient NoC for best effort communication

P Wolkotte, G Smit, J Becker - International Conference on …, 2005 - ieeexplore.ieee.org
A Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for Multi-
Processor System-on-Chip (MPSoC) architectures. In an earlier paper we proposed a …

Improving data cache performance with integrated use of split caches, victim cache and stream buffers

A Naz, M Rezaei, K Kavi, P Sweany - … of the 2004 workshop on MEmory …, 2004 - dl.acm.org
In our prior work we explored a cache organization providing architectural support for
distinguishing between memory references that exhibit spatial and temporal locality and …

[PDF][PDF] 面向复用成本优化的构件重构方法

王忠杰, 徐晓飞, 战德臣 - 软件学报, 2005 - jos.org.cn
构件需要在其复用期间进行持续的优化改进和重构, 消除设计需求与复用需求之间的差异,
在保证有用∗ Supported by the National Natural Science Foundation of China No. 60573086 …

[PDF][PDF] A Study of Separate Array and Scalar Caches.

A Naz, KM Kavi, PH Sweany, M Rezaei - HPCS, 2004 - engold.ui.ac.ir
In our prior work we explored the use of a separate cache for I-structure memories within the
context of dataflow based multithreaded systems. I-structure memories in dataflow systems …

The application of two-level cache in RAID system

C Yun, Y Genke, W Zhiming - … of the 4th World Congress on …, 2002 - ieeexplore.ieee.org
In a RAID system, the cache is one of the important factors that can affect general system
performance. As a two-level cache usually brings better performance than a one-level cache …

A highly fault detectable cache architecture for dependable computing

HR Zarandi, SG Miremadi - … on Computer Safety, Reliability, and Security, 2004 - Springer
Abstract Information integrity in cache memories is a fundamental requirement for
dependable computing. As caches comprise much of a CPU chip area and transistor counts …