In this study, we present a controllability measure for high-level circuit descriptions and a
high-level synthesis-for-testability technique. Unlike many studies in the area of high-level …

This paper presents a non-scan design-for-testability technique applicable to register-
transfer (RT) level data path circuits, which are usually very hard-to-test due to the presence …

The paper discusses techniques that help a designer to consider testability features early in
the design cycle. The behavioral specification of a design is used to perform high level …

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Non-scan design-for-testability methods for making register-transfer-level data path circuits
testable include using EXU S-graph representation of the circuits. Loops in the EXU S-graph …

We present a new clock-control DFT technique for sequential circuits, based on clock
partitioning and selective clock freezing, and we use it to break the global feedback loops …

Behavioral specification of a VLSI design can be used to suggest behavioral modifications
that improve testability of the design. Past work has been targeted at identifying the …

A new synthesis-for-testability approach is proposed that uses control points at branch
conditions to improve testability. Hard-to-control loops are identified through analysis of the …

Per-test fault diagnosis has become an effective methodology for the identification of
complex defects. In this paper, we improve a recent per-test technique by applying …

The causal connection between input circuit representation and the quality of the synthesis
result is investigated, with special attention to the LEKU examples of Cong and Minkovich. It …