FireSim: FPGA-accelerated cycle-exact scale-out system simulation in the public cloud

S Karandikar, H Mao, D Kim, D Biancolin… - 2018 ACM/IEEE 45th …, 2018 - ieeexplore.ieee.org
We present FireSim, an open-source simulation platform that enables cycle-exact
microarchitectural simulation of large scale-out clusters by combining FPGA-accelerated …

{HybCache}: Hybrid {Side-Channel-Resilient} caches for trusted execution environments

G Dessouky, T Frassetto, AR Sadeghi - 29th USENIX Security …, 2020 - usenix.org
Modern multi-core processors share cache resources for maximum cache utilization and
performance gains. However, this leaves the cache vulnerable to side-channel attacks …

A survey of cache bypassing techniques

S Mittal - Journal of Low Power Electronics and Applications, 2016 - mdpi.com
With increasing core-count, the cache demand of modern processors has also increased.
However, due to strict area/power budgets and presence of poor data-locality workloads …

Banshee: Bandwidth-efficient DRAM caching via software/hardware cooperation

X Yu, CJ Hughes, N Satish, O Mutlu… - Proceedings of the 50th …, 2017 - dl.acm.org
Placing the DRAM in the same package as a processor enables several times higher
memory bandwidth than conventional off-package DRAM. Yet, the latency of in-package …

Space: locality-aware processing in heterogeneous memory for personalized recommendations

H Kal, S Lee, G Ko, WW Ro - 2021 ACM/IEEE 48th Annual …, 2021 - ieeexplore.ieee.org
Personalized recommendation systems have become a major AI application in modern data
centers. The main challenges in processing personalized recommendation inferences are …

Hardware/software cooperative caching for hybrid DRAM/NVM memory architectures

H Liu, Y Chen, X Liao, H Jin, B He, L Zheng… - Proceedings of the …, 2017 - dl.acm.org
Non-Volatile Memory (NVM) has recently emerged for its nonvolatility, high density and
energy efficiency. Hybrid memory systems composed of DRAM and NVM have the best of …

Mempod: A clustered architecture for efficient and scalable migration in flat address space multi-level memories

A Prodromou, M Meswani, N Jayasena… - … Symposium on High …, 2017 - ieeexplore.ieee.org
In the near future, die-stacked DRAM will be increasingly present in conjunction with off-chip
memories in hybrid memory systems. Research on this subject revolves around using the …

Chameleon: A dynamically reconfigurable heterogeneous memory system

JB Kotra, H Zhang, AR Alameldeen… - 2018 51st Annual …, 2018 - ieeexplore.ieee.org
Modern computing systems and applications have growing demand for memories with
higher bandwidth. This demand can be alleviated using fast, large on-die or die-stacked …

Pageseer: Using page walks to trigger page swaps in hybrid memory systems

A Kokolis, D Skarlatos… - 2019 IEEE International …, 2019 - ieeexplore.ieee.org
Hybrid main memories composed of DRAM and NonVolatile Memory (NVM) combine the
capacity benefits of NVM with the low-latency properties of DRAM. For highest performance …

[PDF][PDF] Managing Memory Tiers with CXL in Virtualized Environments

Y Zhong, DS Berger, C Waldspurger… - … on Operating Systems …, 2024 - symbioticlab.org
Cloud providers seek to deploy CXL-based memory to increase aggregate memory
capacity, reduce costs, and lower carbon emissions. However, CXL accesses incur higher …