Adaptive estimation of memory cell read thresholds
N Sommer, O Shalvi, U Perlmutter, O Golov… - US Patent …, 2013 - Google Patents
4,661,929 4,768,171 4,811.285 4,899,342 4,910,706 4,993,029 5,056,089 5,077,722
5,126,808 5,163,021 5,172,338 5, 182.558 5, 182,752 5, 191584 5,200,959 5,237,535 …
5,126,808 5,163,021 5,172,338 5, 182.558 5, 182,752 5, 191584 5,200,959 5,237,535 …
Efficient readout from analog memory cells using data compression
U Perlmutter, D Sokolov, O Shalvi, O Golov - US Patent 8,230,300, 2012 - Google Patents
(57) ABSTRACT A method for data storage includes storing data in a group of analog
memory cells by writing respective input storage val ues to the memory cells in the group …
memory cells by writing respective input storage val ues to the memory cells in the group …
Reliable data storage in analog memory cells in the presence of temperature variations
O Shalvi - US Patent 7,773,413, 2010 - Google Patents
A method for data storage includes programming a first group of analog memory cells at a
first time at a known first temperature, so as to cause the analog memory cells in the first …
first time at a known first temperature, so as to cause the analog memory cells in the first …
Combined distortion estimation and error correction coding for memory devices
A method for operating a memory device (24) includes encoding data using an Error
Correction Code (ECC) and storing the encoded data as first analog values in respective …
Correction Code (ECC) and storing the encoded data as first analog values in respective …
Parameter estimation based on error correction code parity check equations
N Sommer - US Patent 8,156,398, 2012 - Google Patents
A method for operating a memory, which includes analog memory cells, includes encoding
data with an Error Correction Code (ECC) that is representable by a plurality of equations …
data with an Error Correction Code (ECC) that is representable by a plurality of equations …
Memory device with internal signap processing unit
D Sokolov, N Sommer, O Shalvi… - US Patent 8,429,493, 2013 - Google Patents
A method for operating a memory (36) includes storing data in a plurality of analog memory
cells (40) that are fabricated on a first semiconductor die by writing input storage values to a …
cells (40) that are fabricated on a first semiconductor die by writing input storage values to a …
Data storage with incremental redundancy
O Shalvi, D Sokolov, E Gurgi, O Golov… - US Patent …, 2012 - Google Patents
A method for operating a memory includes encoding input data with an Error Correction
Code (ECC) to produce input encoded data including first and second sections, such that …
Code (ECC) to produce input encoded data including first and second sections, such that …
Distortion estimation and cancellation in memory devices
(57) ABSTRACT A method for operating a memory (28) includes storing data in a group of
analog memory cells (32) of the memory as respective first Voltage levels. After storing the …
analog memory cells (32) of the memory as respective first Voltage levels. After storing the …
Programming schemes for multi-level analog memory cells
O Shalvi, N Sommer, D Sokolov, Y Kasorla - US Patent 8,259,497, 2012 - Google Patents
A method for data storage includes storing first data bits in a set of multi-bit analog memory
cells at a first time by programming the memory cells to assume respective first programming …
cells at a first time by programming the memory cells to assume respective first programming …
Memory device with reduced reading latency
D Sokolov, G Semo, O Shalvi - US Patent 7,593,263, 2009 - Google Patents
(57) ABSTRACT A method for data storage includes providing a memory, which includes
first memory cells having a first reading latency and second memory cells having a second …
first memory cells having a first reading latency and second memory cells having a second …