The shared last-level caches in CMPs play an important role in improving application
performance and reducing off-chip memory bandwidth requirements. In order to use LLCs …

Cache management policies such as replacement, bypass, or shared cache partitioning
have been relying on data reuse behavior to predict the future. This paper proposes a new …

Spin-Transfer Torque Random Access Memory (STT-RAM) has been identified as an
advantageous candidate for on-chip memory technology due to its high density and ultra low …

Much prior work has studied cache replacement, but a large gap remains between theory
and practice. The design of many practical policies is guided by the optimal policy, Belady's …

Cache hierarchies are increasingly non-uniform and difficult to manage. Several techniques,
such as scratchpads or reuse hints, use static information about how programs access data …

For the sake of higher cell density while achieving near-zero standby power, recent research
progress in Magnetic Tunneling Junction (MTJ) devices has leveraged Multi-Level Cell …

The effectiveness of the last-level shared cache is crucial to the performance of a multi-core
system. In this paper, we observe and make use of the DelinquentPC-Next-Use …

Contention for shared cache resources has been recognized as a major bottleneck for
multicores--especially for mixed workloads of independent applications. While most modern …

Cache replacement policies typically use some form of statistics on past access behavior. As
a common limitation, however, the extent of the history being recorded is limited to either just …

This paper presents an energy-efficient exclusive last-level cache design based on STT-
RAM, which is an emerging memory technology that has higher density and lower static …