To meet the ever-growing need for performance in silicon devices, SoC providers have been
increasingly relying on software-hardware cooperation. By controlling hardware resources …

This paper presents a novel design of an integrated 12-bit multi-channel single-slope ramp
analog-to-digital converter (ADC) for a small animal positron emission tomography (PET) …

Deep learning and signal processing are closely correlated in many IoT scenarios such as
anomaly detection to empower intelligence of things. Many IoT processors utilize digital …

This paper presents an all-digital delay-locked loop with the novel digital delay line for high-
speed memory interface applications. The proposed digital delay line has smaller tuning …

In this thesis we evaluate software-based hardware attacks, a novel attack family that targets
connected devices such as IoT products, smartphones or cloud datacenters. These attacks …

Multiphase delay-locked loop (MP-DLL) is a technique employed in DDR memory
controllers to achieve the required fixed timing delay (tSD) for deskew functionality …

摘要双倍数据速率(Double Data Rate, DDR) DRAM 由于其速度快, 容量大, 而且价格便宜,
在各种需求大量数据缓存的场合得到了广泛使用. 论文介绍了DDR 器件的基本工作原理及需 …

Variations in I/Q gains, phases, and filters of the RF frontend, namely frequency-dependent
I/Q imbalance (FDI), are an important factor in OFDM-based wireless access. To enable the …

This paper reports an 8-phase reset-free antiharmonic delay-locked loop (DLL). The
proposed design overcomes the false and harmonic lock problems by applying the phase …

A fast-lock and portable all-digital delay-locked loop (ADDLL) with 90◦ phase shift and
tunable digitally-controlled phase shifter (DCPS) for DDR controller applications are …