A nonplanar semiconductor device and its method of fabrication is described. The nonplanar
semiconductor device includes a semiconductor body having a top surface opposite a …

Self-aligned contacts for transistors and methods for fabricating the contacts are described.
An etch resistant material is patterned to create an opening that resides above a transistor …

A contact architecture for nanoscale channel devices having contact structures coupling to
and extending between source or drain regions of a device having a plurality of parallel …

US7479421B2 - Process for integrating planar and non-planar CMOS transistors on a bulk
substrate and article made thereby - Google Patents US7479421B2 - Process for integrating …

According to an embodiment of the present invention, a hard mask material is formed on a
silicon film having a global crystal orientation wherein the semiconductor film has a first …

Methods and resulting structure of implementing a compensating implant that creates more
compensation doping as the gate length is increased are disclosed. In particular, the …

A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is
formed over a gallium arsenide substrate. Source-drain extensions are implanted into the …

US8193567B2 - Process for integrating planar and non-planar CMOS transistors on a bulk
substrate and article made thereby - Google Patents US8193567B2 - Process for integrating …

2003-06-27 Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
reassignment SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ASSIGNMENT OF …

A transistor having a narrow bandgap semiconductor source/drain region is described. The
transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon …