Monolithic three dimensional integration of semiconductor integrated circuits
Y Du - US Patent 9,177,890, 2015 - Google Patents
(57) ABSTRACT A three-dimensional integrated circuit comprising top tier nanowire
transistors formed on a bottom tier of CMOS tran sistors, with inter-tier vias, intra-tier vias …
transistors formed on a bottom tier of CMOS tran sistors, with inter-tier vias, intra-tier vias …
3D floorplanning using 2D and 3D blocks
The disclosed embodiments are directed to systems and method for floorplanning an
integrated circuit design using a mix of 2D and 3D blocks that provide a significant …
integrated circuit design using a mix of 2D and 3D blocks that provide a significant …
Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods
Y Du - US Patent 9,536,840, 2017 - Google Patents
(57) ABSTRACT A three-dimensional (3-D) integrated circuit (3DIC) with a graphene shield
is disclosed. In certain embodiments, at least a graphene layer is positioned between two …
is disclosed. In certain embodiments, at least a graphene layer is positioned between two …
Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related methods
Y Du, J Xie, K Samadi - US Patent 9,041,448, 2015 - Google Patents
Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related
method are disclosed. In one embodiment, a single clock source is provided for the 3DIC …
method are disclosed. In one embodiment, a single clock source is provided for the 3DIC …
Data transfer across power domains
J Xie, Y Du - US Patent 8,984,463, 2015 - Google Patents
The disclosed embodiments comprise a multi-stage circuit operating across different power
domains. The multi-stage circuit may be implemented as a master-slave flip-flop circuit …
domains. The multi-stage circuit may be implemented as a master-slave flip-flop circuit …
Clock distribution network for 3D integrated circuit
5,724,557 A* 3/1998 McBean, Sr.................. T16, 113 2011/O121366 A1 5/2011 Or-Bach et
al. 6,040,203 A 3/2000 Bozso et al. 2011/0215300 A1 9, 2011 Guo et al. 6,125,217 A 9 …
al. 6,040,203 A 3/2000 Bozso et al. 2011/0215300 A1 9, 2011 Guo et al. 6,125,217 A 9 …
Security and vulnerability implications of 3D ICs
Physical limit of transistor miniaturization has driven chip design into the third dimension. 3D
integration technology emerges as a viable option to improve chip performance and …
integration technology emerges as a viable option to improve chip performance and …
TSV-based 3-D ICs: Design methods and tools
Vertically integrated circuits (3-D ICs) may revitalize Moore's law scaling which has slowed
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …
An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem
Meeting clock skew constraint is one of the most important tasks in the synthesis of clock
trees. Moreover, the problem becomes much hard to tackle as the delay of clock signals …
trees. Moreover, the problem becomes much hard to tackle as the delay of clock signals …
Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods
J Xie, Y Du - US Patent 9,171,608, 2015 - Google Patents
Abstract A three-dimensional (3D) memory cell separation among 3D integrated circuit
(IC)(3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also …
(IC)(3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also …