Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

The power consumption of integrated circuits is one of the most problematic considerations
affecting the design of high-performance chips and portable devices. The study of power …

Coupling effects between on-chip interconnects must be addressed in ultra deep submicron
VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is …

System-Level Design Techniques for Energy-Efficient Embedded Systems addresses the
development and validation of co-synthesis techniques that allow an effective design of …

We propose instruction code compression as an efficient method for reducing power on an
embedded system. Our approach is the first one to measure and optimize the power …

Dynamic voltage selection and adaptive body biasing have been shown to reduce dynamic
and leakage power consumption effectively. In this paper, we optimally solve the combined …

System optimization techniques are widely used to improve energy efficiency as well as
overall performance. Dynamic voltage scaling (DVS) is well studied and known to be …

For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-
level on-chip communication architecture is emerging as a significant source of power …

A data-distribution and bus-structure aware methodology for the design of coding schemes
for low-power on-chip and interchip communication is presented. A general class of coding …

After a brief introduction to low-power VLSI design, the design space of ASIP instruction set
architectures (ISAs) is introduced with a special focus on important features for digital signal …