Image and video compression standards: algorithms and architectures

V Bhaskaran, K Konstantinides - 1997 - books.google.com
New to the Second Edition: offers the latest developments in standards activities (JPEG-LS,
MPEG-4, MPEG-7, and H. 263) provides a comprehensive review of recent activities on …

Self-tested self-synchronization circuit for mesochronous clocking

F Mu, C Svensson - IEEE Transactions on circuits and systems …, 2001 - ieeexplore.ieee.org
In large-scale and high-speed systems, global synchronization has been commonly used to
protect clocked I/O from data read failure caused by metastability. There are many …

Signal integrity problems in deep submicron arising from interconnects between cores

P Nordholz, D Treytnar, J Otterstedt… - … . 16th IEEE VLSI Test …, 1998 - ieeexplore.ieee.org
The SIA Roadmap shows a very aggressive drive to deep submicron designs. A significant
corner stone in the industries' ability to utilize this tremendous capabilities is the usage of …

A survey of media processing approaches

A Dasu, S Panchanathan - … on Circuits and Systems for Video …, 2002 - ieeexplore.ieee.org
Multimedia processing is becoming increasingly important with a wide variety of applications
ranging from multimedia cellphones to high-definition interactive television. Media …

Multimedia extensions for a 550-MHz RISC microprocessor

DA Carlson, RW Castelino… - IEEE Journal of Solid …, 1997 - ieeexplore.ieee.org
This paper describes circuits used to implement the motion video instructions (MVI) in the
550-MHz Alpha 21 164PC Microprocessor. The chip is fabricated in a 0.35-/spl mu/m CMOS …

Detecting bridging faults in dynamic CMOS circuits

JTY Chang, EJ McCluskey - Digest of Papers IEEE …, 1997 - ieeexplore.ieee.org
New methods for detecting bridging faults in dynamic CMOS circuits are proposed. We show
that resistive shorts in CMOS dynamic circuits can cause intermittent failures and reliability …

The alpha 21164PC microprocessor

P Bannon, Y Saito - … IEEE COMPCON 97. Digest of Papers, 1997 - ieeexplore.ieee.org
The internal architecture of a 2000 MIPS/1000 MFLOPS (peak) high performance low cost
CMOS Alpha microprocessor chip is described. This implementation is derived from the …

Standard-cell-based design methodology for high-performance support chips

B Kick, U Baur, J Koehl, T Ludwig… - IBM journal of research …, 1997 - ieeexplore.ieee.org
We describe the methodology used for the design of a set of CMOS support chips used in
the IBM S/390® Parallel Enterprise Server Generations 3 and 4. The logic design is based …

Multi-media Extensions in Super-pipelined Micro-architectures. A new case for SIMD processing?

M Ferretti - Proceedings Fifth IEEE International Workshop on …, 2000 - ieeexplore.ieee.org
General purpose microprocessors have long been considered a computing platform
unsuited to image processing and vision tasks. The so-called Von-Neumann paradigm and …

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications

H Kubosawa, H Takahashi, S Ando… - IEEE Journal of Solid …, 1998 - ieeexplore.ieee.org
We have designed a microprocessor that is based on a single instruction multiple data
stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia …