[HTML][HTML] Miniaturization of CMOS
HH Radamson, X He, Q Zhang, J Liu, H Cui, J Xiang… - Micromachines, 2019 - mdpi.com
When the international technology roadmap of semiconductors (ITRS) started almost five
decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) …
decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) …
[HTML][HTML] Field-free approaches for deterministic spin–orbit torque switching of the perpendicular magnet
All-electrical driven magnetization switching attracts much attention in next-generation
spintronic memory and logic devices, particularly in magnetic random-access memory …
spintronic memory and logic devices, particularly in magnetic random-access memory …
Technology prospects for data-intensive computing
K Akarvardar, HSP Wong - Proceedings of the IEEE, 2023 - ieeexplore.ieee.org
For many decades, progress in computing hardware has been closely associated with
CMOS logic density, performance, and cost. As such, slowdown in 2-D scaling, frequency …
CMOS logic density, performance, and cost. As such, slowdown in 2-D scaling, frequency …
Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node
V Vashishtha, LT Clark - Microelectronics Journal, 2021 - Elsevier
In this paper, bulk CMOS finFET, horizontal gate-all-around (GAA) nanowire and nanosheet
field-effect transistors are compared for the 5 nm technology node. The performance of …
field-effect transistors are compared for the 5 nm technology node. The performance of …
Reduction of process variations for sub-5-nm node fin and nanosheet FETs using novel process scheme
Process (systematic) variations of sub-5-nm node fin field-effect transistors (FinFETs) and
nanosheet field-effect transistors (NSFETs) were investigated thoroughly using fully …
nanosheet field-effect transistors (NSFETs) were investigated thoroughly using fully …
Sensitivity of source/drain critical dimension variations for sub-5-nm node fin and nanosheet FETs
Source/drain (S/D) variations in sub-5-nm node fin and nanosheet field-effect transistors
(NSFETs) were thoroughly analyzed by using fully calibrated technology computer-aided …
(NSFETs) were thoroughly analyzed by using fully calibrated technology computer-aided …
Effect of temperature on performance of 5-nm node silicon nanosheet transistors for analog applications
This work investigates the effects of temperature on the performance of a 5-nm node N-
channel Nanosheet Transistor (NST) for analog applications. A fully calibrated commercial …
channel Nanosheet Transistor (NST) for analog applications. A fully calibrated commercial …
[HTML][HTML] Investigation of Source/Drain Recess Engineering and Its Impacts on FinFET and GAA Nanosheet FET at 5 nm Node
D Wang, X Sun, T Liu, K Chen, J Yang, C Wu, M Xu… - Electronics, 2023 - mdpi.com
Impacts of source/drain (S/D) recess engineering on the device performance of both the gate-
all-around (GAA) nanosheet (NS) field-effect transistor (FET) and FinFET have been …
all-around (GAA) nanosheet (NS) field-effect transistor (FET) and FinFET have been …
Source/drain extension doping engineering for variability suppression and performance enhancement in 3-nm node FinFETs
P Lu, B Colombeau, S Hung, W Li… - … on Electron Devices, 2021 - ieeexplore.ieee.org
In this article, variability suppression and performance enhancement through source/drain
extension (SDE) module engineering is demonstrated in 3-nm node fin field-effect …
extension (SDE) module engineering is demonstrated in 3-nm node fin field-effect …
Source/drain patterning FinFETs as solution for physical area scaling toward 5-nm node
A novel and feasible process scheme to downsize the source/drain (S/D) epitaxy of 5-nm
node bulk fin-shaped field-effect transistors (FinFETs) were introduced by using fully …
node bulk fin-shaped field-effect transistors (FinFETs) were introduced by using fully …