The interpretation and application of Rent's rule

P Christie, D Stroobandt - … on Very Large Scale Integration (VLSI …, 2000 - ieeexplore.ieee.org
This paper provides a review of both Rent's rule and the placement models derived from it. It
is proposed that the power-law form of Rent's rule, which predicts the number of terminals …

System-level performance evaluation of three-dimensional integrated circuits

A Rahman, R Reif - IEEE transactions on very large scale …, 2000 - ieeexplore.ieee.org
In this paper, the wire (interconnect)-length distribution of three-dimensional (3-D) integrated
circuits (ICs) is derived using Rent's rule and following the methodology used to estimate …

Wiring requirement and three-dimensional integration technology for field programmable gate arrays

A Rahman, S Das, AP Chandrakasan… - IEEE Transactions on …, 2003 - ieeexplore.ieee.org
In this paper, analytical models for predicting interconnect requirements in field-
programmable gate arrays (FPGAs) are presented, and opportunities for three-dimensional …

Generating synthetic benchmark circuits for evaluating CAD tools

D Stroobandt, P Verplaetse… - IEEE Transactions on …, 2000 - ieeexplore.ieee.org
For the development and evaluation of computer-aided design tools for partitioning,
floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits …

Scalable, reconfigurable routers

ESH Tse-Au - US Patent 7,330,468, 2008 - Google Patents
A multi-path router includes an interface module (IM) having a time-sensitive logical
processing path and a non-time-sensitive logical processing path and a special needs …

Designing a 3-D FPGA: switch box architecture and thermal issues

A Gayasen, V Narayanan, M Kandemir… - IEEE transactions on …, 2008 - ieeexplore.ieee.org
Three-dimensional (3-D) integration is an attractive technology to reduce wirelengths in a
field-programmable gate array (FPGA). However, it suffers from two problems: one, the inter …

Exploiting sub-graph isomorphism and probabilistic neural networks for the detection of hardware Trojans at RTL

F Demrozi, R Zucchelli… - 2017 IEEE International …, 2017 - ieeexplore.ieee.org
Hardware Trojans (HTs) have been generally inserted at the lower levels of the digital
system design and fabrication process, where, due to the high complexity of the hardware …

Low-cost microoptical modules for MCM level optical interconnections

C Debaes, M Vervaeke, V Baukens… - IEEE Journal of …, 2003 - ieeexplore.ieee.org
A multichannel free-space microoptical module for dense MCM-level optical
interconnections has been designed and fabricated. Extensive modeling proves that the …

OPSnet: design and demonstration of an asynchronous high-speed optical packet switch

D Klonidis, CT Politi, R Nejabati… - Journal of lightwave …, 2005 - ieeexplore.ieee.org
This paper presents the results of the optical packet switched network (OPSnet) project,
which investigated the design of an asynchronous optical packet switch suitable for the core …

Router having dual propagation paths for packets

ESH Tse-Au - US Patent 8,238,743, 2012 - Google Patents
(*) Notice: Subject to any disclaimer, the term of this 758. R 3. A........................... 398, 25
patent is extended or adjusted under 35 7,626,986 B1 12/2009 Tse-Au USC 154 (b) by 197 …