Topological metal MoP nanowire for interconnect
The increasing resistance of copper (Cu) interconnects for decreasing dimensions is a major
challenge in continued downscaling of integrated circuits beyond the 7 nm technology node …
challenge in continued downscaling of integrated circuits beyond the 7 nm technology node …
Topological semimetals for advanced node interconnects
The continuous miniaturization of transistors has significantly advanced semiconductor
technology, enabling faster and more efficient integrated circuits (ICs). However, this …
technology, enabling faster and more efficient integrated circuits (ICs). However, this …
Vapor phase synthesis of topological semimetal MoP2 nanowires and their resistivity
Topological semimetals (TSMs) possess topologically protected surface states near the
Fermi level with high carrier densities and high mobilities, holding distinct potential for low …
Fermi level with high carrier densities and high mobilities, holding distinct potential for low …
From interconnect materials and processes to chip level performance: Modeling and design for conventional and exploratory concepts
V Huang, D Shim, H Simka… - 2020 IEEE International …, 2020 - ieeexplore.ieee.org
We survey latest device and interconnect scaling trends in literature and present an in-detail
sensitivity analysis of advanced metallization and barrier/liner fabrication methods at a …
sensitivity analysis of advanced metallization and barrier/liner fabrication methods at a …
Adapting interconnect technology to multigate transistors for optimum performance
Beyond the 22-nm technology node, interconnect parasitics are increasingly contributing to
the degradation of circuit performance. Thus, the focus is on optimizing interconnect …
the degradation of circuit performance. Thus, the focus is on optimizing interconnect …
[HTML][HTML] Resistivity scaling of porous MoP narrow lines
The resistivity scaling of copper (Cu) interconnects with decreasing dimensions remains a
major challenge in the downscaling of integrated circuits. Molybdenum phosphide (MoP) is …
major challenge in the downscaling of integrated circuits. Molybdenum phosphide (MoP) is …
Full chip impact study of power delivery network designs in gate-level monolithic 3-D ICs
In this paper, we present a comprehensive study on the impact of power delivery network
(PDN) on full-chip wirelength, routability, power, and thermal effects in gate-level monolithic …
(PDN) on full-chip wirelength, routability, power, and thermal effects in gate-level monolithic …
Modeling and benchmarking back end of the line technologies on circuit designs at advanced nodes
Interconnect scaling has become an ever-growing challenge as the industry advances to
ever smaller nodes. In this work we present a comprehensive framework to quantify the …
ever smaller nodes. In this work we present a comprehensive framework to quantify the …
Bandwidth enhancement of flip-flops using feedback for high-speed integrated circuits
This brief presents a high-speed inductorless D flip-flop (DFF) architecture that works on the
principle of equalization using two feedbacks. Feedback from the first latch output to the …
principle of equalization using two feedbacks. Feedback from the first latch output to the …
Modeling interconnect variability at advanced technology nodes and potential solutions
The advent of multigate transistor technology for 20-nm technology node and beyond, has
increased the importance of wire parasitics, in particular, wire resistance in determining the …
increased the importance of wire parasitics, in particular, wire resistance in determining the …