From the future Si technology perspective: Challenges and opportunities

K Kim - 2010 International Electron Devices Meeting, 2010 - ieeexplore.ieee.org
As silicon technology enters sub-20nm nodes, new materials, structures and processes are
being introduced in order to continue with the advantages of dimensional scaling, eg, 3D …

Oxides, oxides, and more oxides: high-κ oxides, ferroelectrics, ferromagnetics, and multiferroics

N Izyumskaya, Y Alivov, H Morkoç - Critical Reviews in Solid State …, 2009 - Taylor & Francis
We review and critique the recent developments on multifunctional oxide materials, which
are gaining a good deal of interest. Recongnizing that this is a vast area, the focus of this …

Method of forming crystallographically stabilized doped hafnium zirconium based films

RD Clark - US Patent 7,833,913, 2010 - Google Patents
A method is provided for forming doped hafnium zirconium based films by atomic layer
deposition (ALD) or plasma enhanced ALD (PEALD). The method includes disposing a …

Ultimate scaling of high-κ gate dielectrics: Higher-κ or interfacial layer scavenging?

T Ando - Materials, 2012 - mdpi.com
Current status and challenges of aggressive equivalent-oxide-thickness (EOT) scaling of
high-κ gate dielectrics via higher-κ (> 20) materials and interfacial layer (IL) scavenging …

High-κ dielectrics and advanced channel concepts for Si MOSFET

M Wu, YI Alivov, H Morkoç - Journal of Materials Science: Materials in …, 2008 - Springer
With scaling of the gate length downward to increase speed and density, the gate dielectric
thickness must also be reduced. However, this practice which has been in effect for many …

Defect Passivation With Fluorine and Interface Engineering for Hf-Based High- /Metal Gate Stack Device Reliability and Performance Enhancement

HH Tseng, PJ Tobin, S Kalpat… - … on Electron Devices, 2007 - ieeexplore.ieee.org
Using a fluorinated high-fc/metal gate stack combined with a stress relieved preoxide
(SRPO) pretreatment before high-fc deposition, we show significant device reliability and …

Semiconductor device containing a buried threshold voltage adjustment layer and method of forming

RD Clark, GJ Leusink - US Patent 7,772,073, 2010 - Google Patents
Recent advances in microelectronics have included the use of high-k films in gate stacks for
logic applications. These high-k films often include hafnium (Hf) and/or zirconium (Zr) based …

Electrical and Reliability Characteristics of FinFETs With High-k Gate Stack and Plasma Treatments

YL Li, KS Chang-Liao, CC Li, CH Huang… - … on Electron Devices, 2020 - ieeexplore.ieee.org
Effects of high-kgate stacks and plasma treatments on electrical and reliability characteristics
of FinFET were comprehensively studied in this work. A higher ONcurrent, higher ON-/OFF …

Hybrid gate last integration scheme for multi-layer high-k gate stacks

RD Clark - US Patent 8,865,581, 2014 - Google Patents
A method for manufacturing a dual workfunction semiconductor device using a hybrid gate
last integration scheme is described. According to one embodiment, the method includes …

Cyclic Plasma Treatment during ALD Hf1-xZrxO2 Deposition

MN Bhuyian, D Misra, K Tapily, RD Clark… - ECS Journal of Solid …, 2014 - iopscience.iop.org
Abstract Effect of slot plane antenna (SPA) Ar plasma on the reliability of intermediate
plasma (DSDS) treated ALD Hf 1-x Zr x O 2 samples with x= 0, 0.31, 0.8 were investigated …