A 2 GHz direct digital frequency synthesizer (DDFS) chip-set is presented which operates at
a very low supply voltage of 2 V. The chip-set consists of a CMOS DDFS LSI which …

A 1-V power supply low-power and high-speed 16-b fixed-point digital signal processor
using a 0.5-/spl mu/m process has been developed for mobile phone applications. A 1-V …

In this paper, we present the characterization and design of energy-efficient, on chip cache
memories. The characterization of power dissipation in on-chip cache memories reveals that …

The principles and design of current sense amplifiers for low-voltage MOS memories are
described. The low input impedance of current sense amplifiers is explained using a simple …

To optimize performance and power of a processor's cache, a multiple-divided module
(MDM) cache architecture is proposed to save power at memory peripherals as well as the …

A system level approach for a memory power reduction is proposed in this paper. The basic
idea is allocating frequently executed object codes into a small subprogram memory and …

V ultra low-power SRAM circuit techniques are described for word-bit configurable memory
macrocells. A shared bitline SRAM cell architecture with modified address assignment is …

An architectural level technique for a high performance and low energy cache memory is
proposed in this paper. The key idea of our approach is to divide a cache memory into …

We present results of characterization of power dissipation in on-chip cache memories.
Details of power dissipated in different sub-circuits are presented. These results reveal that …

The radiation induced soft errors have become one of the most important and challenging
failure mechanisms in modern electronic devices. This paper proposes a new circuit level …