[HTML][HTML] Understanding fault-tolerance vulnerabilities in advanced SoC FPGAs for critical applications
The emergence of heterogeneous FPGA-based SoCs and their growing complexity fueled
by the introduction of various accelerators bring the reliability aspect of these systems to the …
by the introduction of various accelerators bring the reliability aspect of these systems to the …
Evaluating soft core RISC-V processor in SRAM-based FPGA under radiation effects
AB de Oliveira, LA Tambara… - … on Nuclear Science, 2020 - ieeexplore.ieee.org
This article evaluates the RISC-V Rocket processor embedded in a Commercial Off-The-
Shelf (COTS) SRAM-based field-programmable gate array (FPGA) under heavy-ions …
Shelf (COTS) SRAM-based field-programmable gate array (FPGA) under heavy-ions …
[HTML][HTML] A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays
W Wang, X Li, L Chen, H Sun, F Zhang - Sensors, 2024 - mdpi.com
Aerospace-grade SRAM-based field-programmable gate arrays (FPGAs) used in space
applications are highly susceptible to single event effects, leading to soft errors in FPGAs …
applications are highly susceptible to single event effects, leading to soft errors in FPGAs …
[HTML][HTML] Novel lockstep-based fault mitigation approach for SoCs with roll-back and roll-forward recovery
Abstract All-Programmable System-on-Chips (APSoCs) constitute a compelling option for
employing applications in radiation environments thanks to their high-performance …
employing applications in radiation environments thanks to their high-performance …
A low-overhead reconfigurable RISC-V quad-core processor architecture for fault-tolerant applications
S Shukla, KC Ray - IEEE Access, 2022 - ieeexplore.ieee.org
Radiation can affect the correct behavior of an electronic device. Hence, the
microprocessors used for space missions need to be protected against fault. TMR (Triple …
microprocessors used for space missions need to be protected against fault. TMR (Triple …
A hierarchical scrubbing technique for SEU mitigation on SRAM-based FPGAs
G He, S Zheng, N Jing - IEEE Transactions on Very Large Scale …, 2020 - ieeexplore.ieee.org
The SRAM-based field-programmable gate array (FPGA) is extremely susceptible to single
event upsets (SEUs) on configuration memory which can lead to soft error and malfunction …
event upsets (SEUs) on configuration memory which can lead to soft error and malfunction …
Hang features of microcontroller exposed to pulsed ionizing radiation
AS Pilipenko, MI Tikhonov - Microelectronics Reliability, 2023 - Elsevier
The results of pulsed ionizing radiation influence on an ARM microcontroller hang behavior
are presented. The hang microcontroller functional blocks data was analyzed using the ARM …
are presented. The hang microcontroller functional blocks data was analyzed using the ARM …
Optical multi-context blind scrubbing for field programmable gate arrays
Y Takaki, M Watanabe - IEEE Photonics Journal, 2020 - ieeexplore.ieee.org
This paper presents a proposal of a new optical multi-context blind scrubbing that can not
only increase the soft-error tolerance of the configuration memory of field programmable …
only increase the soft-error tolerance of the configuration memory of field programmable …
[PDF][PDF] FPGA 三模冗余工具的关键技术与发展
陈雷， 张瑶伟， 王硕， 周婧， 田春生， 庞永江， 马筱婧… - 电子与信息学报, 2022 - jeit.ac.cn
SRAM 型现场可编程门阵列(FPGA) 在空间辐射环境中容易受到单粒子效应的影响,
从而发生软错误, 三模冗余技术(TMR) 是目前使用最广泛的缓解FPGA 软错误的电路加固技术 …
从而发生软错误, 三模冗余技术(TMR) 是目前使用最广泛的缓解FPGA 软错误的电路加固技术 …
Impact of TMR design layouts on single event tolerance in SRAM-based FPGAs
H Wang, Y Wang, W Wang - Microelectronics Reliability, 2021 - Elsevier
For highly reliable applications in mission critical systems, the Triple Modular Redundancy
(TMR) technique is believed to be a common and effective approach to mitigate Single …
(TMR) technique is believed to be a common and effective approach to mitigate Single …