Results from the coldflux superconductor integrated circuit design tool project

CJ Fourie, K Jackman, J Delport… - IEEE Transactions …, 2023 - ieeexplore.ieee.org
In five and a half years, the ColdFlux project under the IARPA SuperTools program pushed
the boundaries of digital and analog superconductor electronic design automation (S-EDA) …

Challenges and Unexplored Frontiers in Electronic Design Automation for Superconducting Digital Logic

S Razmkhah, RS Aviles, M Li, S Gupta… - … , Automation & Test …, 2024 - ieeexplore.ieee.org
Positioned as a highly promising post-CMOS computing technology, superconductor
electronics (SCE) offer the potential for unparalleled performance and energy efficiency …

Design for testability (dft) for rsfq circuits

M Li, Y Lin, S Gupta - 2023 IEEE 41st VLSI Test Symposium …, 2023 - ieeexplore.ieee.org
Superconducting electronics (SCE), especially Rapid Single Flux Quantum (RSFQ) logic, is
being developed due to its high-performance and low power. In [1]–[3], we developed new …

Striking a good balance between area and throughput of RSFQ circuits containing feedback loops

M Li, B Zhang, M Pedram - IEEE Transactions on Applied …, 2023 - ieeexplore.ieee.org
Electronic design automation solutions are being developed to support the synthesis and
physical design optimization of Rapid Single Flux Quantum (RSFQ) logic circuits with …

Built in self test (BIST) for RSFQ circuits

M Li, Y Lin, S Gupta - 2024 IEEE 42nd VLSI Test Symposium …, 2024 - ieeexplore.ieee.org
In the era beyond the end of physical scaling of CMOS, growing attention is being paid to
Superconducting electronics (SCE), especially Rapid Single Flux Quantum (RSFQ) logic …

Longest Path Selection Based on Path Identifiers

I Pomeranz - IEEE Access, 2024 - ieeexplore.ieee.org
A small delay defect adds a small extra delay to the propagation time of a signal through a
gate or line. Small delay defects can occur during fabrication or during the lifetime of a chip …

Path Unselection for Path Delay Fault Test Generation

I Pomeranz - IEEE Transactions on Very Large Scale …, 2022 - ieeexplore.ieee.org
Path selection procedures identify path delay faults whose tests detect small delay defects.
Path selection criteria are positive in the sense that they point to paths that should be …

[PDF][PDF] Results from the ColdFlux Superconductor Integrated Circuit Design Tool Project

P Beerel, S Gupta, H Zha, S Razmkhah… - researchgate.net
In five and a half years, the ColdFlux project under the IARPA SuperTools program pushed
the boundaries of digital and analog superconductor electronic design automation (S-EDA) …